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    Electrostatic chuck including declamping electrode and method of declamping
    21.
    发明授权
    Electrostatic chuck including declamping electrode and method of declamping 有权
    静电吸盘，包括电极和放电方法

    公开(公告)号：US09101038B2

    公开(公告)日：2015-08-04

    申请号：US14136826

    申请日：2013-12-20

    Applicant: Lam Research Corporation

    Inventor： Harmeet Singh ,  Christopher Kimball ,  Keith Gaff ,  Tyler Gloski

    IPC: H01L21/683 ,  H01T23/00 ,  H05F3/02

    CPC classification number: H01L21/6833

    Abstract: A semiconductor wafer processing apparatus for processing semiconductor wafers comprises a semiconductor wafer processing chamber in which a semiconductor wafer is processed, a process gas source in fluid communication with the processing chamber adapted to supply process gas into the processing chamber, a vacuum source adapted to exhaust process gas and byproducts of the processing from the processing chamber, and an electrostatic chuck assembly. The electrostatic chuck assembly comprises a support surface in a layer of ceramic material on which the semiconductor wafer is supported during processing of the wafer in the chamber, at least one electrostatic clamping electrode embedded in the layer of ceramic material, the at least one electrostatic clamping electrode operable to apply an electrostatic clamping force to the wafer on the support surface when an electrostatic clamping voltage is applied to the clamping electrode, and at least one declamping electrode embedded in the layer of ceramic material above the at least one electrostatic clamping electrode operable to provide a path for draining any residual charge between the wafer and the support surface when the electrostatic clamping voltage is no longer applied to the clamping electrode.

    Abstract translation: 一种用于处理半导体晶片的半导体晶片处理装置，包括处理半导体晶片的半导体晶片处理室，与处理室流体连通的处理气体源，其适于将处理气体供应到处理室中，适于排出的真空源 来自处理室的处理气体和副产物以及静电吸盘组件。 静电卡盘组件包括在陶瓷材料层中的支撑表面，其中半导体晶片在腔室中的晶片处理期间被支撑，至少一个静电夹持电极嵌入在陶瓷材料层中，该至少一个静电夹持 电极，其可操作以当静电钳位电压施加到所述夹持电极时将静电夹持力施加到所述支撑表面上的所述晶片;以及至少一个在所述至少一个静电夹持电极上方的陶瓷材料层中的所述电极， 当静电钳位电压不再施加到夹紧电极时，提供用于在晶片和支撑表面之间排出任何残留电荷的路径。

    CONTROLLING CD AND CD UNIFORMITY WITH TRIM TIME AND TEMPERATURE ON A WAFER BY WAFER BASIS
    22.
    发明申请
    CONTROLLING CD AND CD UNIFORMITY WITH TRIM TIME AND TEMPERATURE ON A WAFER BY WAFER BASIS 有权
    通过基于波浪的方式控制光盘和光盘的平均时间和温度

    公开(公告)号：US20150053347A1

    公开(公告)日：2015-02-26

    申请号：US14470544

    申请日：2014-08-27

    Applicant: Lam Research Corporation

    Inventor： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

    IPC: H01L21/66 ,  H01L21/67

    CPC classification number: H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer. The current wafer as subjected to a trimming operation for a duration of the target trim time while controlling temperatures in the temperature control zones to thereby control temperature of each device die location based on the target temperature profile.

    Abstract translation: 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据。 控制器还接收等离子体室中要处理的当前晶片的关键器件参数。 控制器基于至少一个先前处理的晶片的过程控制和温度数据以及当前晶片的关键器件参数来计算当前晶片的目标修整时间和目标温度分布。 当前的晶片在控制温度控制区域中的温度的同时进行修整操作，同时控制温度控制区域中的温度，从而基于目标温度分布来控制每个器件管芯位置的温度。

    CONTROLLING CD AND CD UNIFORMITY WITH TRIM TIME AND TEMPERATURE ON A WAFER BY WAFER BASIS
    24.
    发明申请
    CONTROLLING CD AND CD UNIFORMITY WITH TRIM TIME AND TEMPERATURE ON A WAFER BY WAFER BASIS 有权
    通过基于波浪的方式控制光盘和光盘的平均时间和温度

    公开(公告)号：US20140220709A1

    公开(公告)日：2014-08-07

    申请号：US13758266

    申请日：2013-02-04

    Applicant: LAM RESEARCH CORPORATION

    Inventor： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

    IPC: H01L21/66 ,  H01L21/67

    CPC classification number: H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.

    Abstract translation: 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据，以及在等离子体室中待处理的当前晶片的关键器件参数。 控制器基于过程控制和温度数据以及关键设备参数来计算当前晶片的目标修整时间和目标温度分布。 在目标修整时间期间修剪当前晶片，同时基于目标温度分布来控制每个器件管芯位置的温度。

    Electrostatic Chuck design for cooling-gas light-up prevention
    27.
    发明授权
    Electrostatic Chuck design for cooling-gas light-up prevention 有权

    公开(公告)号：US11651991B2

    公开(公告)日：2023-05-16

    申请号：US17334639

    申请日：2021-05-28

    Applicant: Lam Research Corporation

    Inventor： Alexander Matyushkin ,  Alexei Marakhtanov ,  John Patrick Holland ,  Keith Gaff ,  Felix Kozakevich

    IPC: H01L21/687 ,  H01L21/683 ,  H01L21/67 ,  H01J37/32

    CPC classification number: H01L21/68785 ,  H01J37/32091 ,  H01J37/32183 ,  H01J37/32568 ,  H01J37/32577 ,  H01J37/32724 ,  H01L21/67109 ,  H01L21/6833

    Abstract: A wafer support structure in a chamber of a semiconductor manufacturing apparatus is provided. The wafer support structure includes a dielectric block having a bottom surface and a top surface supports a wafer when present. The wafer support structure includes a baseplate for supporting the dielectric block. The wafer support structure includes a first electrode embedded in an upper part of the dielectric block. The first electrode is proximate and below the top surface of the dielectric block. A top surface of the first electrode is substantially parallel to the top surface of the dielectric block. The first electrode is configured for connection to a direct current (DC) power source. The wafer support structure includes a second electrode embedded in the dielectric block. The wafer support structure includes a second electrode disposed below the first electrode and a separation distance is defined between the first electrode and the second electrode within the dielectric block. The wafer support structure includes a radio frequency (RF) gasket provides an electrical connection between the second electrode and the a baseplate.

    Electrostatic chuck design for cooling-gas light-up prevention
    30.
    发明授权
    Electrostatic chuck design for cooling-gas light-up prevention 有权

    公开(公告)号：US10083853B2

    公开(公告)日：2018-09-25

    申请号：US14887166

    申请日：2015-10-19

    Applicant: Lam Research Corporation

    Inventor： Alexander Matyushkin ,  Alexei Marakhtanov ,  John Patrick Holland ,  Keith Gaff ,  Felix Kozakevich

    IPC: H01L21/687 ,  H01L21/683 ,  H01L21/67

    CPC classification number: H01L21/68785 ,  H01L21/67109 ,  H01L21/6833

    Abstract: An Electrostatic Chuck (ESC) in a chamber of a semiconductor manufacturing apparatus is presented for eliminating cooling-gas light-up. One wafer support includes a baseplate connected to a radiofrequency power source, a dielectric block, gas supply channels for cooling the wafer bottom, and first and second electrodes. The dielectric block is situated above the baseplate and supports the wafer when present. The first electrode is embedded in the top half of the dielectric block, where the top surface of the first electrode is substantially parallel to a top surface of the dielectric block, and the first electrode is connected to a DC power source. Further, the second electrode is embedded in a bottom half of the dielectric block, the second electrode being electrically connected to the first electrode, where the bottom surface of the second electrode is substantially parallel to a top surface of the baseplate.

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