公开(公告)号：US20220078915A1

公开(公告)日：2022-03-10

申请号：US17012817

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Seng Kim Ye ,  Hong Wan Ng ,  Hem P. Takiar

IPC: H05K1/18 ,  H01L25/065 ,  H01L23/13 ,  H01L23/498 ,  H01L23/64

Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.

公开(公告)号：US11189548B2

公开(公告)日：2021-11-30

申请号：US15627076

申请日：2017-06-19

Applicant: Micron Technology, Inc.

Inventor： Ai-Chie Wang ,  Choon Kuan Lee ,  Chin Hui Chong ,  Wuu Yean Tay

IPC: H01L23/495 ,  H01L23/00

Abstract: Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers.

公开(公告)号：US10211114B2

公开(公告)日：2019-02-19

申请号：US15702225

申请日：2017-09-12

Applicant: Micron Technology, Inc.

Inventor： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

IPC: H01L23/053 ,  H01L25/065 ,  H01L25/11 ,  H01L23/00 ,  H01L25/07 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L21/66

Abstract: Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an interposer substrate with a plurality of interposer contacts. A microelectronic die is attached and electrically coupled to the interposer substrate. The device further includes a casing covering the die and at least a portion of the interposer substrate. A plurality of electrically conductive through-casing interconnects are in contact with and projecting from corresponding interposer contacts at a first side of the interposer substrate. The through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing. The through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to the first side of the interposer substrate.

公开(公告)号：US09355992B2

公开(公告)日：2016-05-31

申请号：US14450998

申请日：2014-08-04

Applicant: Micron Technology, Inc.

Inventor： Lee Choon Kuan ,  David J. Corisis ,  Chin Hui Chong

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L24/92 ,  H01L22/14 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/49531 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92127 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die. Terminal pads of the interposer substrate may be electrically connected to either or both of a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. Additional components, active, passive or both, may be connected to pads of the two-dimensional array to provide a system-in-a-package. Lead fingers of a lead frame may be superimposed on the opposing side of the interposer substrate, bonded directly to the land grid array land and wire bonded to pads as desired for repair or to ease routing problems on the interposer. The land grid array package may be mounted to a carrier substrate, and the lands wire bonded to conductive pads on the carrier substrate. Methods of fabrication are also disclosed.

Abstract translation: 半导体器件封装包括焊盘栅格阵列封装。 至少一个半导体管芯安装到插入器衬底上，其中半导体管芯的接合焊盘连接到与至少一个半导体管芯在内插器衬底的同一侧上的端子焊盘。 插入器基板的端子焊盘可以电连接到焊盘的外围阵列图案中的一个或两个以及中心的二维阵列阵列图案，两个阵列图案位于至少从中间层基板的相对侧起至少 一个半导体芯片。 可以将主动，被动或两者的附加组件连接到二维阵列的焊盘以提供系统级封装。 引线框架的引脚可以叠置在插入器基板的相对侧上，直接接合到焊盘栅格阵列焊盘，并且焊接到焊盘上，以便修理或者简化插入器上的布线问题。 焊盘阵列封装可以安装到载体衬底上，焊盘引线键合到载体衬底上的导电焊盘上。 还公开了制造方法。

公开(公告)号：US09084360B2

公开(公告)日：2015-07-14

申请号：US13866713

申请日：2013-04-19

Applicant: Micron Technology, Inc.

Inventor： David J. Corisis ,  Choon Kuan Lee ,  Chin Hui Chong

IPC: H05K1/11 ,  G01R31/02 ,  H05K1/02 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/66 ,  G06F1/16 ,  H05K1/18 ,  H05K3/42

CPC classification number: H05K1/115 ,  G01R31/026 ,  G06F1/16 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0221 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0296 ,  H05K1/18 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/09809 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.

Abstract translation: 电子器件包括具有在衬底中或衬底上延伸的第一和第二对导电迹线的衬底。 第一导电互连构件延伸穿过衬底中的孔并且与第一和第二对中的每一个的第一迹线电连通，而第二导电互连构件延伸穿过孔并与第一导电互连构件中的每一个的第二迹线电连通 和第二对。 第一和第二互连构件彼此间隔开距离，该距离基本上等于分隔每对导电迹线的距离。 电子设备组件包括被配置为通过导电结构将差分信号传输到接收设备的发送设备。 导电结构包括第一和第二对导电迹线，其中第一和第二互连构件之间提供电连通。

公开(公告)号：US20140162412A1

公开(公告)日：2014-06-12

申请号：US14180567

申请日：2014-02-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chin Hui Chong ,  David J. Corisis ,  Choon Kuan Lee

IPC: H01L21/48 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L21/4857 ,  H01L23/50 ,  H01L24/82 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an integrated circuit that is operatively coupled to the interposer. A method is disclosed which includes obtaining an interposer having at least one capacitor formed at least partially within an opening in the interposer and operatively coupling an integrated circuit to the interposer. A method is also disclosed which includes obtaining an interposer comprising a dielectric material, forming an opening in the interposer and forming a capacitor that is positioned at least partially within the opening.

Abstract translation: 公开了一种包括插入器的至少一个电容器，至少部分地形成在插入器中形成的开口内的至少一个电容器和可操作地耦合到插入器的集成电路。 公开了一种方法，其包括获得具有至少部分地在插入器中的开口内形成的至少一个电容器并且将集成电路可操作地耦合到插入器的插入器。 还公开了一种方法，其包括获得包括电介质材料的插入件，在插入器中形成开口并形成至少部分位于开口内的电容器。

公开(公告)号：US20140141572A1

公开(公告)日：2014-05-22

申请号：US14165855

申请日：2014-01-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chin Hui Chong ,  Hong Wan Ng

IPC: H05K3/30 ,  H05K3/34 ,  H05K3/10

CPC classification number: H05K3/303 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/06156 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H05K3/10 ,  H05K3/34 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

Abstract translation: 下面描述具有多层基板的半导体组件和相关制造方法的各种实施例。 在一个实施例中，用于承载半导体管芯的衬底包括第一路由级别，第二路由级别以及第一和第二路由级别之间的导电通路。 导电通孔具有接近第一路由级的第一端和靠近第二路由级的第二端。 第一路由级别包括端子和导体通孔的端子与第一端之间的第一迹线。 第二路由级别包括导电通孔的第二端和球场之间的第二迹线。 第一路由级别的终端和第二路由级别的球点都可以从基板的同一侧进行电连接。

公开(公告)号：US20130249092A1

公开(公告)日：2013-09-26

申请号：US13893638

申请日：2013-05-14

Applicant: Micron Technology, Inc.

Inventor： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/24 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Packaged microelectronic devices recessed in support member cavities, and associated methods, are disclosed. Method in accordance with one embodiment includes positioning a microelectronic device in a cavity of a support member, with the cavity having a closed end with a conductive layer, and an opening through which the cavity is assessable. The microelectronic device can have bond sites, a first surface, and a second surface facing opposite from the first surface. The microelectronic device can be positioned in the cavity so that the second surface faces toward and is carried by the conductive layer. The method can further include electrically coupling the bond sites of the microelectronic device to the conductive layer. In particular embodiments, the microelectronic device can be encapsulated in the cavity without the need for a releasable tape layer to temporarily support the microelectronic device.

Abstract translation: 封装在支撑构件空腔中的微电子器件以及相关方法被公开。 根据一个实施例的方法包括将微电子器件定位在支撑构件的空腔中，其中空腔具有带有导电层的封闭端以及空腔可以评估的开口。 微电子器件可以具有接合位置，第一表面和与第一表面相对的第二表面。 微电子器件可以定位在空腔中，使得第二表面面向导电层并由导电层承载。 该方法还可以包括将微电子器件的键合位置电耦合到导电层。 在具体实施例中，微电子器件可以被封装在空腔中，而不需要可释放的带层来临时支撑微电子器件。

公开(公告)号：US20130235517A1

公开(公告)日：2013-09-12

申请号：US13866713

申请日：2013-04-19

Applicant: MICRON TECHNOLOGY, INC

Inventor： David J. Corisis ,  Choon Kuan Lee ,  Chin Hui Chong

IPC: H05K1/11 ,  G06F1/16 ,  H05K1/18

CPC classification number: H05K1/115 ,  G01R31/026 ,  G06F1/16 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0221 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0296 ,  H05K1/18 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/09809 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.

公开(公告)号：US20250149416A1

公开(公告)日：2025-05-08

申请号：US18920479

申请日：2024-10-18

Applicant: Micron Technology, Inc.

Inventor： Faxing Che ,  Amirul Afiq Bin Hud ,  Darren Tan Hong Suang ,  Hong Wang Ng ,  Soon Sing Ng ,  Chin Hui Chong

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/66 ,  H01L23/00 ,  H01L23/552 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate and a semiconductor device. The substrate includes a first conductive layer, the first conductive layer having a first trace with a first exposed pad and a second trace with a second exposed pad. A wire bond runs above the first conductive layer to connect the first exposed pad to the second exposed pad, such that the first trace and the second trace are only connected via the wire bond. The semiconductor device includes an electrical connection to the first trace.