公开(公告)号：US20050124091A1

公开(公告)日：2005-06-09

申请号：US10978521

申请日：2004-11-02

申请人： Katsuya Fukase ,  Toyoaki Sakai

发明人： Katsuya Fukase ,  Toyoaki Sakai

IPC分类号： H01L21/48 ,  H05K3/06 ,  H05K3/20 ,  H01L21/44 ,  H01L21/425 ,  H01L21/50 ,  H01L21/82

CPC分类号： H05K3/064 ,  H01L21/4821 ,  H01L21/4828 ,  H01L21/4846 ,  H05K3/062 ,  H05K3/202 ,  H05K2203/0369 ,  H05K2203/0508 ,  H05K2203/058 ,  H05K2203/0597 ,  H05K2203/1476

摘要： A process for forming a metal pattern comprising the following steps of: (a) half-etching a metal plate from one or respective sides thereof by means of first masking which is positioned on one or respective surfaces of the metal plate; (b) applying positive liquid resist on the half-etched metal plate from one or respective sides of the first masking; (c) exposing the positive liquid resist with light from one or respective sides of the first masking; (d) developing the positive liquid resist in such a manner that unexposed positive liquid resist located under the first masking is protected and exposed, uncured liquid resist is removed; (e) half-etching again the metal plate from one or respective sides thereof by means of second masking composed of the first masking and the protected positive liquid resist; (f) repeating the steps (b) to (e) until a metal pattern is obtained from the metal plate; and (g) removing the first masking, and the second or subsequent masking of the unexposed positive liquid resist, from the metal plate.

摘要翻译： 一种用于形成金属图案的方法，包括以下步骤：（a）通过位于金属板的一个或相应表面上的第一掩模从其一侧或两侧半蚀刻金属板; （b）从第一掩模的一个或相应的两侧向半蚀刻的金属板施加正的液体抗蚀剂; （c）用来自第一掩模的一个或相应侧面的光曝光正极液体抗蚀剂; （d）以防止位于第一掩模下面的未曝光的正性液体抗蚀剂被保护和暴露的方式显影出正的液体抗蚀剂，去除未固化的液体抗蚀剂; （e）通过由第一掩模和受保护的正性液体抗蚀剂组成的第二掩模，从其一侧或两侧再次对金属板进行蚀刻; （f）重复步骤（b）至（e），直到从金属板获得金属图案; 和（g）从金属板去除未曝光的正性液体抗蚀剂的第一掩蔽和第二次或随后的掩蔽。

公开(公告)号：US5909053A

公开(公告)日：1999-06-01

申请号：US761360

申请日：1996-12-09

申请人： Katsuya Fukase ,  Takahiro Iijima ,  Masao Nakazawa ,  Shinichi Wakabayashi

发明人： Katsuya Fukase ,  Takahiro Iijima ,  Masao Nakazawa ,  Shinichi Wakabayashi

IPC分类号： H01L23/50 ,  H01L21/48 ,  H01L23/495 ,  H05K3/20 ,  H05K3/34

CPC分类号： H01L21/4821 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/181 ,  H05K3/20 ,  H05K3/202 ,  H05K3/205 ,  H05K3/3421

摘要： In a method for manufacturing a lead frame, a predetermined pattern is formed on a matrix 10 by a resist, an electro-deposition portion is provided in a cavity formed in the resist patterns 12, and the electrodeposition pattern 13 is separated from the matrix 10. The resist pattern is formed on the matrix 10 so that a cavity portion 17 connecting a plurality of cavity 16 ends for inner lead formation can be included in the resist pattern, and an electro-deposition portion is provided into the cavity portion 17 so that the electro-deposition pattern 13 can be formed into a configuration in which the tip ends of the inner leads 22 are connected by a connecting piece 21, and the electro-deposition pattern 13 is separated from the matrix 10 while the tip ends of the inner leads 22 are connected by the connecting piece 21.

摘要翻译： 在制造引线框架的方法中，通过抗蚀剂在矩阵10上形成预定图案，在形成于抗蚀图案12中的空腔中设置电沉积部分，并将电沉积图案13从矩阵10分离 抗蚀剂图形形成在矩阵10上，使得连接多个腔体16的端部用于内部引线形成的空腔部分17可以包括在抗蚀剂图案中，并且将电沉积部分设置到空腔部分17中，使得 电沉积图案13可以形成为通过连接片21连接内部引线22的前端的结构，并且电沉积图案13与基体10分离，同时内部引线22的顶端 引线22由连接片21连接。

公开(公告)号：US08186053B2

公开(公告)日：2012-05-29

申请号：US12271519

申请日：2008-11-14

申请人： Kishio Yokouchi ,  Hideaki Yoshimura ,  Katsuya Fukase

发明人： Kishio Yokouchi ,  Hideaki Yoshimura ,  Katsuya Fukase

IPC分类号： H01K3/10 ,  B22F7/00

CPC分类号： H01L23/49822 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/056 ,  H05K3/426 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0281 ,  H05K2201/0323 ,  H05K2201/0347 ,  H05K2201/0959 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/12035 ,  H01L2224/0401

摘要： A circuit board has plated through holes which are laid out with a fine pitch and meets requirements relating to characteristics such as strength and thermal expansion coefficient. A method of manufacturing a circuit board includes: a step of forming a core portion by thermal compression bonding prepregs formed by disposing carbon fibers so as to produce openings at positions where plated through holes will pass through and impregnating the carbon fibers with resin; a step of forming through holes that pass inside the openings at positions of the openings in the core portion; and a step of forming a conductive layer on inner surfaces of the through holes to form plated through holes at positions that do not interfere with the carbon fibers and thereby produce a core substrate.

摘要翻译： 电路板具有以细间距布置的电镀通孔，并且满足与强度和热膨胀系数等特性有关的要求。 一种电路板的制造方法，其特征在于，包括：通过热压缩形成芯部的步骤，通过设置碳纤维形成的预浸料，以在电镀通孔穿过的位置处产生开口，并用树脂浸渍碳纤维; 在芯部的开口部的位置形成贯通孔内的通孔的工序; 以及在通孔的内表面上形成导电层的步骤，在不干扰碳纤维的位置处形成电镀通孔，从而制造芯基板。

公开(公告)号：US08143533B2

公开(公告)日：2012-03-27

申请号：US12227377

申请日：2006-05-17

申请人： Yasuo Kaneda ,  Munetoshi Irisawa ,  Yuji Toyoda ,  Toyokazu Komuro ,  Katsuya Fukase ,  Toyoaki Sakai

发明人： Yasuo Kaneda ,  Munetoshi Irisawa ,  Yuji Toyoda ,  Toyokazu Komuro ,  Katsuya Fukase ,  Toyoaki Sakai

IPC分类号： H05K1/03

CPC分类号： H05K3/426 ,  H05K1/116 ,  H05K3/002 ,  H05K3/108 ,  H05K2201/09545 ,  H05K2203/0191 ,  H05K2203/0574 ,  H05K2203/1184 ,  H05K2203/1394

摘要： There are provided a method for forming a resist pattern for preparing a circuit board having a landless or small-land-width through-hole(s) to realize a high-density circuit board, a method for producing a circuit board, and a circuit board. A method for forming a resist pattern, comprising the steps of forming a resin layer and a mask layer on a first surface of a substrate having a through-hole(s), and removing the resin layer on the through-hole(s) and on a periphery of the through-hole(s) on the first surface by supplying a resin layer removing solution from a second surface opposite to the first surface of the substrate, and a method for producing a circuit board using the method for forming a resist pattern, and a circuit board.

摘要翻译： 提供了一种形成抗蚀剂图案的方法，该抗蚀剂图案用于制备具有无轨或小地平面宽度的通孔的电路板，以实现高密度电路板，生产电路板的方法和电路 板。 一种形成抗蚀剂图案的方法，包括以下步骤：在具有通孔的基板的第一表面上形成树脂层和掩模层，并且除去通孔上的树脂层和 通过从与基板的第一表面相对的第二表面提供树脂层去除溶液，在第一表面的通孔的周边上，以及使用该抗蚀剂形成方法制造电路板的方法 图案和电路板。

公开(公告)号：US07679004B2

公开(公告)日：2010-03-16

申请号：US10598524

申请日：2005-03-02

申请人： Katsuya Fukase ,  Toyoaki Sakai ,  Munetoshi Irisawa ,  Toyokazu Komuro ,  Yasuo Kaneda ,  Masanori Natsuka ,  Wakana Aizawa

发明人： Katsuya Fukase ,  Toyoaki Sakai ,  Munetoshi Irisawa ,  Toyokazu Komuro ,  Yasuo Kaneda ,  Masanori Natsuka ,  Wakana Aizawa

IPC分类号： H01R12/04 ,  H05K1/00

CPC分类号： H05K3/064 ,  H05K1/116 ,  H05K3/0094 ,  H05K3/061 ,  H05K3/065 ,  H05K3/108 ,  H05K3/421 ,  H05K3/427 ,  H05K2201/09381 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/098 ,  H05K2203/0517 ,  H05K2203/0577 ,  H05K2203/0582 ,  H05K2203/1184 ,  H05K2203/1394

摘要： As means for solving a problem of a positional shift of a land and a hole which is caused by an alignment in the formation of an etching resist layer and a plated resist layer in a method of manufacturing a circuit board, there are provided a method of manufacturing a circuit board including the steps of forming a first resin layer on a surface of an insulating substrate having a conductive layer on the surface and an internal wall of a through hole or/and a non-through hole, forming a second resin layer which is insoluble or slightly soluble in a developing solution for the first resin layer on the first resin layer provided on the surface conductive layer, and removing the first resin layer provided over the hole with the developing solution for the first resin layer, and a method of manufacturing a circuit board including the step of uniformly charging a surface of the first resin layer to induce a potential difference to the first resin layer provided over the hole and the first resin layer provided on the surface conductive layer before forming the second resin layer. Moreover, there is provided a circuit board having a hole with a small positional shift and high precision.

摘要翻译： 作为在电路基板的制造方法中解决在形成抗蚀剂层和电镀抗蚀剂层时的取向引起的焊盘和孔的位置偏移的问题的方法，提供了一种方法， 制造电路板，包括以下步骤：在表面上具有导电层的绝缘基板的表面上形成第一树脂层和通孔或/或非通孔的内壁，形成第二树脂层，所述第二树脂层 在设置在表面导电层上的第一树脂层上的第一树脂层的显影液中不溶或微溶，用第一树脂层的显影液除去设在孔上的第一树脂层， 制造电路板，包括对第一树脂层的表面均匀充电以对设置在孔上的第一树脂层引起电位差的步骤， 在形成第二树脂层之前，在表面导电层上设置阴极层。 此外，提供一种电路板，其具有位置偏移小且精度高的孔。

公开(公告)号：US07415762B2

公开(公告)日：2008-08-26

申请号：US11488648

申请日：2006-07-19

申请人： Katsuya Fukase ,  Shinichi Wakabayashi

发明人： Katsuya Fukase ,  Shinichi Wakabayashi

IPC分类号： H01K3/10

CPC分类号： H01L23/147 ,  H01L21/6835 ,  H01L23/14 ,  H01L23/3677 ,  H01L23/492 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/0401

摘要： An interposer to be interposed between a semiconductor chip to be mounted thereon and a packaging board has an interposer portion made of a semiconductor and an interposer portion provided around the foregoing interposer portion integrally therewith. On both surfaces of the interposer portions, wiring patterns are formed via insulating layers. The wiring patterns are electrically connected via through holes formed at required positions in the interposer portions. The outer interposer portion is made of an insulator or a metal body. Further, external connection terminals are bonded to one surface of the interposer.

摘要翻译： 要安装在其上的半导体芯片和封装板之间的插入件具有由半导体制成的插入部分和与其一体设置在上述插入部分周围的插入部分。 在内插器部分的两个表面上，经由绝缘层形成布线图案。 布线图案通过形成在插入件部分中的所需位置的通孔电连接。 外部插入部由绝缘体或金属体构成。 此外，外部连接端子被接合到插入器的一个表面。

公开(公告)号：US20070017090A1

公开(公告)日：2007-01-25

申请号：US11486820

申请日：2006-07-13

申请人： Toyoaki Sakai ,  Katsuya Fukase

发明人： Toyoaki Sakai ,  Katsuya Fukase

IPC分类号： H01B13/00 ,  H05K3/00

CPC分类号： H05K3/064 ,  C23F1/02 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/062 ,  H05K3/202 ,  H05K2203/0369 ,  H05K2203/0508 ,  H05K2203/058 ,  H05K2203/0597 ,  H05K2203/1184 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T29/49124 ,  H01L2924/00

摘要： A method of forming a high aspect ratio metal plate pattern and a circuit board by multi-stage etching with a metal mask is disclosed. A resist (12) is coated on one of two surfaces of a copper plate (10) and patterned to form a resist pattern. A tin plating layer (14) is formed using this resist pattern, and with this tin plating layer as a mask, the copper plate is selectively half etched. By coating, exposing and developing the positive resist (18), the side etched portion under the tin plating layer is protected by the positive resist. With the tin plating layer and the protective resist layer as a mask, the half etching is executed again. This process is repeated until the resist and the tin plating layer used as a mask are finally removed to produce a metal pattern (20).

摘要翻译： 公开了一种通过金属掩模的多级蚀刻形成高纵横比金属板图案和电路板的方法。 抗蚀剂（12）涂覆在铜板（10）的两个表面中的一个上并被图案化以形成抗蚀剂图案。 使用该抗蚀剂图案形成锡镀层（14），以该镀锡层为掩模，选择性地对铜板进行半蚀刻。 通过涂覆，曝光和显影正性抗蚀剂（18），镀锡层下面的侧蚀刻部分被正性抗蚀剂保护。 以镀锡层和保护层为掩模，再次进行半蚀刻。 重复该过程，直到最终除去用作掩模的抗蚀剂和锡镀层以产生金属图案（20）。

公开(公告)号：US5643433A

公开(公告)日：1997-07-01

申请号：US172286

申请日：1993-12-23

申请人： Katsuya Fukase ,  Takahiro Iijima ,  Masao Nakazawa ,  Shinichi Wakabayashi

发明人： Katsuya Fukase ,  Takahiro Iijima ,  Masao Nakazawa ,  Shinichi Wakabayashi

IPC分类号： H01L23/50 ,  H01L21/48 ,  H01L23/495 ,  H05K3/20 ,  H05K3/34 ,  C25D1/00

CPC分类号： H01L21/4821 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/181 ,  H05K3/20 ,  H05K3/202 ,  H05K3/205 ,  H05K3/3421

摘要： A method for manufacturing a lead frame employing a resist pattern formed on a matrix and having a cavity therein, in which an electro-deposition pattern is formed. A connecting cavity portion interconnects tip ends of inner lead cavity portions such that a connecting portion interconnects the tip ends of inner leads of the electro-deposition pattern formed in the cavity. The connecting piece is maintained while the electro-deposition pattern is separated from the matrix and the resist.

摘要翻译： 一种制造引线框架的方法，该引线框采用形成在基体上并在其中形成有空穴的抗蚀剂图案，其中形成电沉积图案。 连接腔部分将内部引线腔部分的末端互连，使得连接部分将形成在腔中的电沉积图案的内部引线的末端相互连接。 当电沉积图案与基体和抗蚀剂分离时，保持连接件。

公开(公告)号：US4867839A

公开(公告)日：1989-09-19

申请号：US240213

申请日：1988-09-06

申请人： Takeshi Sato ,  Katsuya Fukase ,  Kiyotaka Shimada ,  Hirofumi Uchida

发明人： Takeshi Sato ,  Katsuya Fukase ,  Kiyotaka Shimada ,  Hirofumi Uchida

IPC分类号： B29C45/37 ,  H01L21/56 ,  H05K3/18 ,  H05K3/38

CPC分类号： H01L21/565 ,  B29C45/372 ,  H05K3/381 ,  H01L2924/0002 ,  H01L2924/15312 ,  H05K2203/1152 ,  H05K3/181 ,  Y10T29/49158

摘要： A process for forming a circuit substrate comprising placing an electrodeposited metal foil having a rough surface provided with a large number of fine projections in a cavity of a mold in such a manner that the rough surface faces an inside of the mold cavity; pouring a melting resin into the mold cavity to form a molded article; peeling the metal foil from the molded article to form a large number of fine concavities corresponding to the projections; electroless-plating the resin base to form a metal film; and photoetching to form a circuit pattern on the resin base.

摘要翻译： 一种形成电路基板的方法，包括将具有大量微细突起的粗糙表面的电沉积金属箔放置在模具的空腔中，使粗糙表面面对模腔内; 将熔融树脂浇注到模腔中以形成模制品; 从成形品剥离金属箔，形成与突起对应的大量细小凹部; 对树脂基底进行化学镀以形成金属膜; 并进行光刻以在树脂基底上形成电路图案。