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    Process for making circuit board or lead frame
    2.
    发明授权
    Process for making circuit board or lead frame 失效
    制造电路板或引线框架的工艺

    公开(公告)号：US07005241B2

    公开(公告)日：2006-02-28

    申请号：US10822825

    申请日：2004-04-13

    申请人： Katsuya Fukase ,  Toyoaki Sakai

    发明人： Katsuya Fukase ,  Toyoaki Sakai

    IPC分类号： G03F7/00

    CPC分类号： G03F7/0035 ,  H01L21/4828 ,  H01L21/4846 ,  H05K3/062 ,  H05K3/064 ,  H05K3/202 ,  H05K2203/0369 ,  H05K2203/0508 ,  H05K2203/058 ,  H05K2203/0597 ,  H05K2203/1476

    摘要： A process for making a circuit board comprises the following steps of: half-etching a metal layer formed on an insulating substrate by means of a first masking which is positioned on an upper surface of the metal layer; applying a positive liquid resist on the half-etched metal layer from an upper side of the first masking; exposing the positive liquid resist with parallel light from the upper side of the first masking and developing the positive liquid resist in such a manner that a part of the positive liquid resist located under the first masking is protected to be unexposed and undeveloped; etching again the metal layer by means of a second masking composed of the first masking and the protected positive liquid resist to form a conductive pattern on the insulating substrate; and removing the first masking and the second masking from the metal layer.

    摘要翻译： 制造电路板的方法包括以下步骤：通过位于金属层的上表面上的第一掩模半蚀刻在绝缘基板上形成的金属层; 从第一掩模的上侧在半蚀刻金属层上施加正的液体抗蚀剂; 以平行的光从第一掩模的上侧露出正的液体抗蚀剂，并以这样的方式显影出正的液体抗蚀剂，使得位于第一掩蔽下的正极抗蚀剂的一部分被保护为未曝光和未显影; 通过由第一掩模和受保护的正性液体抗蚀剂构成的第二掩模再次蚀刻金属层，以在绝缘基板上形成导电图案; 以及从金属层去除第一掩蔽和第二掩蔽。

    Process for design and manufacture of fine line circuits on planarized thin film dielectrics and circuits manufactured thereby
    3.
    发明授权
    Process for design and manufacture of fine line circuits on planarized thin film dielectrics and circuits manufactured thereby 有权
    在平面化薄膜电介质和由此制造的电路上设计和制造细线电路的方法

    公开(公告)号：US06290860B1

    公开(公告)日：2001-09-18

    申请号：US09283679

    申请日：1999-04-01

    申请人： Bernd K. Appelt ,  John M. Lauffer ,  Voya R. Markovich ,  Irving Memis ,  David J. Russell

    发明人： Bernd K. Appelt ,  John M. Lauffer ,  Voya R. Markovich ,  Irving Memis ,  David J. Russell

    IPC分类号： H01B1300

    CPC分类号： H05K3/4652 ,  H05K3/0023 ,  H05K3/0035 ,  H05K2203/0508 ,  H05K2203/0554

    摘要： A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured by photoimaging techniques.

    摘要翻译： 一种电路板，其结构包括适用于通过激光烧蚀，等离子体消融或机械钻孔技术制造通孔的永久可光成像介电材料，以及通过光成像技术。 还公开了一种用于在至少一侧具有第一级电路图案的衬底上制造多电平电路的工艺。 该过程包括在第一级电路图案上施加永久可光成像电介质; 将永久可光成像电介质暴露于辐射; 将导电金属层层叠到电介质上; 通过机械钻孔或通过激光或等离子体消融在导电金属层和电介质中形成孔; 以及制作二级电路图案，并用导电材料填充所述孔，以电连接所述第一和第二层电路。 要求设计多级电路板产品的另一方法包括制造具有上述结构的原型，其中通过机械钻孔或通过激光或等离子体烧蚀制造孔，评估原型，然后制造商业电路板，其具有 基本上与原型相同的结构和结构材料，但是其中孔通过光成像技术制造。

    Method of forming metal plate pattern and circuit board
    4.
    发明申请
    Method of forming metal plate pattern and circuit board 审中-公开
    形成金属板图案和电路板的方法

    公开(公告)号：US20070017090A1

    公开(公告)日：2007-01-25

    申请号：US11486820

    申请日：2006-07-13

    申请人： Toyoaki Sakai ,  Katsuya Fukase

    发明人： Toyoaki Sakai ,  Katsuya Fukase

    IPC分类号： H01B13/00 ,  H05K3/00

    CPC分类号： H05K3/064 ,  C23F1/02 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/062 ,  H05K3/202 ,  H05K2203/0369 ,  H05K2203/0508 ,  H05K2203/058 ,  H05K2203/0597 ,  H05K2203/1184 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T29/49124 ,  H01L2924/00

    摘要： A method of forming a high aspect ratio metal plate pattern and a circuit board by multi-stage etching with a metal mask is disclosed. A resist (12) is coated on one of two surfaces of a copper plate (10) and patterned to form a resist pattern. A tin plating layer (14) is formed using this resist pattern, and with this tin plating layer as a mask, the copper plate is selectively half etched. By coating, exposing and developing the positive resist (18), the side etched portion under the tin plating layer is protected by the positive resist. With the tin plating layer and the protective resist layer as a mask, the half etching is executed again. This process is repeated until the resist and the tin plating layer used as a mask are finally removed to produce a metal pattern (20).

    摘要翻译： 公开了一种通过金属掩模的多级蚀刻形成高纵横比金属板图案和电路板的方法。 抗蚀剂（12）涂覆在铜板（10）的两个表面中的一个上并被图案化以形成抗蚀剂图案。 使用该抗蚀剂图案形成锡镀层（14），以该镀锡层为掩模，选择性地对铜板进行半蚀刻。 通过涂覆，曝光和显影正性抗蚀剂（18），镀锡层下面的侧蚀刻部分被正性抗蚀剂保护。 以镀锡层和保护层为掩模，再次进行半蚀刻。 重复该过程，直到最终除去用作掩模的抗蚀剂和锡镀层以产生金属图案（20）。

    Fabrication method of printed wiring board
    5.
    发明授权
    Fabrication method of printed wiring board 失效
    印刷电路板的制造方法

    公开(公告)号：US5464662A

    公开(公告)日：1995-11-07

    申请号：US300131

    申请日：1994-09-02

    申请人： Tomoo Murakami ,  Takanori Tsunoda

    发明人： Tomoo Murakami ,  Takanori Tsunoda

    IPC分类号： H05K3/24 ,  H05K1/11 ,  H05K3/00 ,  H05K3/06 ,  H05K3/28 ,  H05K3/38 ,  B05D5/12

    CPC分类号： H05K3/0094 ,  H05K1/111 ,  H05K3/28 ,  H05K2201/09745 ,  H05K2201/09881 ,  H05K2203/0353 ,  H05K2203/0369 ,  H05K2203/0508 ,  H05K2203/0574 ,  H05K2203/0759 ,  H05K2203/1394 ,  H05K3/0082 ,  H05K3/061 ,  H05K3/383 ,  Y02P70/611

    摘要： A fabrication method of a printed wiring board in which the halation effect of light irradiated to a solder resist film is utilized in a process of selectively removing the solder resist film. After a conductive layer is patterned to a given circuit pattern including soldering pads, the solder resist film is formed on the base material to cover the patterned conductive layer. The solder resist film is selectively exposed to light utilizing reflection of the irradiated light from the insulating base material and developed so that the solder resist film is selectively left in areas adjacent to the respective soldering pads. Then, an etching resist film is formed to cover the patterned conductive layer except for the soldering pads, and surface areas of the respective soldering pads are selectively etched using the etching resist film as a mask to produce solder resist dams made of the solder resist film left on the base material. Solder films are formed on the respective soldering pads thus selectively etched. Electronic components can be soldered on the soldering pads with satisfactory reliability even if the soldering pads have narrow pitches such as 500 .mu.m or less.

    摘要翻译： 在选择性去除阻焊膜的工序中，利用照射到阻焊膜的光的晕影效果的印刷电路板的制造方法。 在将导电层图案化为包括焊盘的给定电路图案之后，在基底材料上形成阻焊膜以覆盖图案化的导电层。 利用来自绝缘基材的照射光的反射来选择性地将阻焊膜暴露于光，并显影，使得阻焊膜选择性地留在与各个焊盘相邻的区域中。 然后，形成抗蚀剂膜以覆盖除了焊盘之外的图案化导电层，并且使用抗蚀剂膜作为掩模来选择性地蚀刻各个焊盘的表面积，以形成由阻焊膜制成的阻焊堤 留在基材上。 在相应的焊盘上形成焊接膜，从而选择性地蚀刻。 即使焊盘具有500μm以下的窄间距，也可以将电子部件焊接在焊盘上，其可靠性良好。