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公开(公告)号：US10108372B2
公开(公告)日：2018-10-23
申请号：US14605593
申请日：2015-01-26
Applicant: Micron Technology, Inc.
Inventor： Giuseppe D'Eliseo , Graziano Mirichigni , Danilo Caraccio , Luca Porzio , Antonino Pollio
Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.
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公开(公告)号：US20180129424A1
公开(公告)日：2018-05-10
申请号：US15345919
申请日：2016-11-08
Applicant: Micron Technology, Inc.
Inventor： Emanuele Confalonieri , Marco Dallabora , Paolo Amato , Danilo Caraccio , Daniele Balluchi
CPC classification number: G06F3/0611 , G06F3/061 , G06F3/0647 , G06F3/0649 , G06F3/0658 , G06F3/068 , G06F3/0685 , G11C11/005 , G11C13/0002 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/10 , G11C16/26
Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.
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公开(公告)号：US20180039572A1
公开(公告)日：2018-02-08
申请号：US15786408
申请日：2017-10-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Graziano Mirichigni , Danilo Caraccio , Luca Porzio
CPC classification number: G06F12/023 , G06F3/0659 , G06F12/0246 , G06F13/1642
Abstract: Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the memory. The host is configured to provide a plurality of memory access requests to the memory, to request ready status information regarding whether the memory is ready to execute a memory access request of the plurality of memory access requests, and to request execution of the memory access request responsive to the ready status information.
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公开(公告)号：US20170351458A1
公开(公告)日：2017-12-07
申请号：US15685926
申请日：2017-08-24
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Emanuele Confalonieri , Federico Tiziani
CPC classification number: G06F3/0644 , G06F3/0607 , G06F3/0608 , G06F3/0631 , G06F3/0637 , G06F3/0685 , G06F9/5077 , G06F12/0223 , G06F12/0238 , G06F12/0246 , G06F13/385 , G06F2212/2022 , G06F2212/2024 , G06F2213/3804 , G06F2213/3854 , G11C13/0002 , G11C13/0004 , G11C14/009 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.
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公开(公告)号：US20170083260A1
公开(公告)日：2017-03-23
申请号：US14860326
申请日：2015-09-21
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Graziano Mirichigni , Gianfranco Santopietro , Gianfranco Ferrante , Emanuele Confalonieri
IPC: G06F3/06
CPC classification number: G06F3/0643 , G06F3/061 , G06F3/0679
Abstract: A memory device includes a memory component and controller circuitry. The memory component stores data and the controller circuitry receives, from a host electronic device, one or more commands of a memory system protocol. The one or more commands include at least one write command, the write command comprising one or more blocks of data to be stored in the memory component. Further, the one or more commands include metadata, attributes, or both related to the one or more blocks of data. The controller circuitry interprets and executes the one or more commands. Accordingly, the blocks are stored in the memory component. Further, the controller circuitry of the memory device has access to the metadata, attributes or both.
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Patent Agency Ranking
公开(公告)号：US20160085476A1
公开(公告)日：2016-03-24
申请号：US14954507
申请日：2015-11-30
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Emanuele Confalonieri , Federico Tiziani
IPC: G06F3/06
CPC classification number: G06F3/0644 , G06F3/0607 , G06F3/0608 , G06F3/0631 , G06F3/0637 , G06F3/0685 , G06F9/5077 , G06F12/0223 , G06F12/0238 , G06F12/0246 , G06F13/385 , G06F2212/2022 , G06F2212/2024 , G06F2213/3804 , G06F2213/3854 , G11C13/0002 , G11C13/0004 , G11C14/009 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: Various embodiments comprise devices to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one embodiment, the apparatus is to manage commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and map portions of a second memory having the attribute enhanced set through a second interface controller. Additional devices are described.
Abstract translation: 各种实施例包括用于管理多个存储器类型并根据主机指导在存储器设备中重新配置分区的设备。 在一个实施例中，该装置是通过第一接口控制器管理命令，以映射不具有属性增强集合的第一存储器的部分，以及通过第二接口控制器映射具有属性增强集合的第二存储器的部分。 描述附加设备。
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公开(公告)号：US09213603B2
公开(公告)日：2015-12-15
申请号：US14456559
申请日：2014-08-11
Applicant: Micron Technology, Inc.
Inventor： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
Abstract: In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.
Abstract translation: 在各种实施例中，单个虚拟化纠错码（ECC）NAND控制器执行ECC算法并管理NAND闪存堆栈。 虚拟化ECC NAND控制器允许主机处理器作为单个NAND芯片驱动闪存器件堆叠，同时控制器将数据重定向到堆栈中选择的NAND存储器件。 在各种实施例中，控制器管理多个NAND存储器件。 控制器一次为多个NAND存储器件中的一个选择一个供电，以节省存储系统的整体功耗。
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公开(公告)号：US08984370B2
公开(公告)日：2015-03-17
申请号：US13907524
申请日：2013-05-31
Applicant: Micron Technology, Inc.
Inventor： Giovanni Campardo , Stefano Corno , Gian Pietro Vanalli , Manuela Scognamiglio , Danilo Caraccio , Federico Tiziani , Massimiliano Magni , Andrea Ghilardelli
CPC classification number: G11C29/42 , G06F11/1048 , G11C2029/0411
Abstract: A system and method are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores error correction information related to the blocks storing the data. The first memory and the second memory are of different types.
Abstract translation: 公开了一种系统和方法，其中第一非易失性存储器包括存储数据的块和存储与存储数据的块相关的纠错信息的第二存储器。 第一个内存和第二个内存是不同的类型。
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公开(公告)号：US20130332800A1
公开(公告)日：2013-12-12
申请号：US13907524
申请日：2013-05-31
Applicant: Micron Technology, Inc.
Inventor： Giovanni Campardo , Stefano Corno , Gian Pietro Vanalli , Manuela Scognamiglio , Danilo Caraccio , Federico Tiziani , Massimiliano Magni , Andrea Ghilardelli
IPC: G11C29/42
CPC classification number: G11C29/42 , G06F11/1048 , G11C2029/0411
Abstract: A system and method are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores error correction information related to the blocks storing the data. The first memory and the second memory are of different types.
Abstract translation: 公开了一种系统和方法，其中第一非易失性存储器包括存储数据的块和存储与存储数据的块相关的纠错信息的第二存储器。 第一个内存和第二个内存是不同的类型。
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公开(公告)号：US20130268825A1
公开(公告)日：2013-10-10
申请号：US13907669
申请日：2013-05-31
Applicant: Micron Technology, Inc.
Inventor： Giovanni Campardo , Stefano Corno , Gian Pietro Vanalli , Manuela Scognamiglio , Danilo Caraccio , Frederico Tiziani , Massimiliano Magni , Andrea Ghilardelli
IPC: G11C29/42
CPC classification number: G11C29/42 , G06F11/1048 , G11C2029/0411
Abstract: A method and system are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores overhead information related to the blocks storing the data. The amount of the second memory storing the overhead information related to the at least one block of the plurality of blocks is varied.
Abstract translation: 公开了一种方法和系统，其中第一非易失性存储器包括存储数据的块和存储与存储数据的块有关的开销信息的第二存储器。 存储与多个块的至少一个块相关的开销信息的第二存储器的量是变化的。
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