公开(公告)号：US09543503B2

公开(公告)日：2017-01-10

申请号：US15045865

申请日：2016-02-17

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade ,  Sumeet C. Pandey ,  Gurtej S. Sandhu

IPC: H01L29/82 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01L43/08

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic cell includes a magnetic tunnel junction that comprises magnetic and nonmagnetic materials exhibiting hexagonal crystal structures. The hexagonal crystal structure is enabled by a seed material, proximate to the magnetic tunnel junction, that exhibits a hexagonal crystal structure matching the hexagonal crystal structure of the adjoining magnetic material of the magnetic tunnel junction. In some embodiments, the seed material is formed adjacent to an amorphous foundation material that enables the seed material to be formed at the hexagonal crystal structure. In some embodiments, the magnetic cell includes hexagonal cobalt (h-Co) free and fixed regions and a hexagonal boron nitride (h-BN) tunnel barrier region with a hexagonal zinc (h-Zn) seed region adjacent the h-Co. The structure of the magnetic cell enables high tunnel magnetoresistance, high magnetic anisotropy strength, and low damping. Methods of fabrication and semiconductor devices are also disclosed.

Abstract translation: 磁性电池包括磁性隧道结，其包括具有六方晶系结构的磁性和非磁性材料。 六方晶体结构通过靠近磁性隧道结的种子材料实现，其表现出与磁性隧道结相邻的磁性材料的六方晶系结构相匹配的六方晶系结构。 在一些实施方案中，种子材料邻近无定形基底材料形成，使得种子材料能够以六方晶体结构形成。 在一些实施方案中，磁性电池包括六方钴（h-Co）游离和固定区域以及与h-Co相邻的六方锌（h-Zn）种子区域的六方氮化硼（h-BN）隧道势垒区。 磁性单元的结构能够实现高隧道磁阻，高磁各向异性强度和低阻尼。 还公开了制造方法和半导体器件。

公开(公告)号：US20160358641A1

公开(公告)日：2016-12-08

申请号：US15237434

申请日：2016-08-15

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade

IPC: G11C11/24 ,  G11C11/56 ,  H01L49/02 ,  H01L45/00 ,  H01L27/10 ,  G11C11/34 ,  G11C13/00

CPC classification number: G11C11/24 ,  G11C8/08 ,  G11C11/34 ,  G11C11/56 ,  G11C11/565 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  H01L27/101 ,  H01L28/40 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233

Abstract: Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.

公开(公告)号：US09419215B2

公开(公告)日：2016-08-16

申请号：US14557306

申请日：2014-12-01

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade

IPC: G11C11/24 ,  H01L45/00 ,  G11C13/00 ,  G11C11/56 ,  H01L27/10 ,  H01L49/02 ,  G11C11/34

CPC classification number: G11C11/24 ,  G11C8/08 ,  G11C11/34 ,  G11C11/56 ,  G11C11/565 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  H01L27/101 ,  H01L28/40 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233

Abstract: Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.

公开(公告)号：US09349803B2

公开(公告)日：2016-05-24

申请号：US14521088

申请日：2014-10-22

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade ,  Sumeet C. Pandey

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/16 ,  H01L21/02 ,  H01L27/092 ,  H01L29/165 ,  H01L29/78 ,  H01L29/51 ,  H01L29/778

CPC classification number: H01L29/1606 ,  H01L21/02175 ,  H01L21/02527 ,  H01L21/02664 ,  H01L27/092 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66045 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/78 ,  Y02E10/50

Abstract: A semiconducting graphene structure may include a graphene material and a graphene-lattice matching material over at least a portion of the graphene material, wherein the graphene-lattice matching material has a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material. The semiconducting graphene structure may have an energy band gap of at least about 0.5 eV. A method of modifying an energy band gap of a graphene material may include forming a graphene-lattice matching material over at least a portion of a graphene material, the graphene-lattice matching material having a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material.

Abstract translation: 半导体石墨烯结构可以包括在石墨烯材料的至少一部分上的石墨烯材料和石墨烯 - 晶格匹配材料，其中所述石墨烯 - 晶格匹配材料具有在晶格常数的倍数的约±5％内的晶格常数，或 石墨烯材料的粘结长度。 半导体石墨烯结构可以具有至少约0.5eV的能带隙。 修饰石墨烯材料的能带隙的方法可包括在石墨烯材料的至少一部分上形成石墨烯 - 晶格匹配材料，所述石墨烯 - 晶格匹配材料的晶格常数在约±5％ 石墨烯材料的晶格常数或键长度。

公开(公告)号：US09236473B2

公开(公告)日：2016-01-12

申请号：US14277134

申请日：2014-05-14

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade ,  Gurtej S. Sandhu

IPC: G11C11/22 ,  H01L29/78 ,  G11C11/56 ,  G11C13/00 ,  H01L21/28 ,  H01L49/02 ,  H01L29/792 ,  H01L27/06

CPC classification number: H01L29/7841 ,  G11C11/565 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/51 ,  G11C2213/53 ,  G11C2213/77 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/792

Abstract: A memcapacitor device includes a pair of opposing conductive electrodes. A semiconductive material including mobile dopants within a dielectric and a mobile dopant barrier dielectric material are received between the pair of opposing conductive electrodes. The semiconductive material and the barrier dielectric material are of different composition relative one another which is at least characterized by at least one different atomic element. One of the semiconductive material and the barrier dielectric material is closer to one of the pair of electrodes than is the other of the semiconductive material and the barrier dielectric material. The other of the semiconductive material and the barrier dielectric material is closer to the other of the pair of electrodes than is the one of the semiconductive material and the barrier dielectric material. Other implementations are disclosed, including field effect transistors, memory arrays, and methods.

Abstract translation: 电容器装置包括一对相对的导电电极。 包括电介质中的移动掺杂剂和可移动掺杂剂阻挡介电材料的半导体材料被接收在该对相对的导电电极之间。 半导体材料和阻挡介电材料的组成彼此不同，其至少特征在于至少一种不同的原子元素。 半导体材料和阻挡介电材料之一比半导体材料和阻挡介电材料中的另一个更靠近一对电极之一。 半导体材料和阻挡介电材料中的另一个比半导体材料和阻挡介电材料中的一个更接近于该对电极中的另一个。 公开了其他实现方式，包括场效应晶体管，存储器阵列和方法。

公开(公告)号：US20140332751A1

公开(公告)日：2014-11-13

申请号：US14444795

申请日：2014-07-28

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade ,  Bhaskar Srinivasan ,  Gurtej S. Sandhu

IPC: H01L45/00

CPC classification number: H01L45/085 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2213/56 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146

Abstract: Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A stack is formed to have programmable material between first and second electrodes. The programmable material has mobile ions which are moved within the programmable material to transform the programmable material from one memory state to another. An average charge across the moving mobile ions has an absolute value greater than 2. Some embodiments include memory cells with programmable material between first and second electrodes. The programmable material includes an aluminum nitride first layer, and includes a second layer containing a mobile ion species in common with the first layer.

Abstract translation: 一些实施例包括编程存储器单元的方法。 多个电荷载体可以在存储器单元内移动，其中跨越移动电荷载流子的绝对值大于2的平均电荷。一些实施例包括形成和编程基于离子传输的存储单元的方法。 堆叠形成为在第一和第二电极之间具有可编程材料。 可编程材料具有在可编程材料内移动的移动离子，以将可编程材料从一个存储器状态转换到另一个。 移动移动离子上的平均电荷具有大于2的绝对值。一些实施例包括在第一和第二电极之间具有可编程材料的存储单元。 可编程材料包括氮化铝第一层，并且包括含有与第一层共同的可移动离子物质的第二层。

公开(公告)号：US08837212B2

公开(公告)日：2014-09-16

申请号：US14038472

申请日：2013-09-26

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade ,  Gurtej S. Sandhu

IPC: G11C11/14 ,  H05K3/36 ,  H05K1/14 ,  H01L23/00 ,  H05K7/04 ,  G11C11/16 ,  H05K1/11 ,  B82Y99/00 ,  H05K3/34

CPC classification number: H05K1/0298 ,  B82Y99/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  G11C19/0808 ,  H01L24/02 ,  H01L24/80 ,  H01L2224/04042 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K1/112 ,  H05K1/113 ,  H05K1/144 ,  H05K3/3436 ,  H05K3/36 ,  H05K3/4697 ,  H05K7/04 ,  H05K2201/09381 ,  Y10S977/932 ,  Y10T29/49126 ,  Y10T29/49128 ,  H01L2924/00

Abstract: Electronic devices may include a first substrate bearing circuitry components at a nanoscale pitch within the first substrate. The first substrate may include microscale bond pads on a surface of the first substrate. A via may electrically connect one of the microscale bond pads to one of the circuitry components. A second substrate may be electrically connected to at least one of the microscale bond pads. Methods of forming electronic devices may include positioning a first substrate adjacent to a second substrate. The first substrate may bear circuitry components at a nanoscale pitch within the first substrate. The first substrate may include microscale bond pads on a surface of the first substrate. A via may electrically connect one of the microscale bond pads to one of the circuitry components. The second substrate may be electrically connected to at least one of the microscale bond pads.

Abstract translation: 电子器件可以包括第一衬底，其承载在第一衬底内的纳米级间距的电路组件。 第一衬底可以包括在第一衬底的表面上的微结构焊盘。 通孔可以将微型接合焊盘之一电连接到电路部件之一。 第二衬底可以电连接到至少一个微结构焊盘。 形成电子器件的方法可以包括将邻近第二衬底的第一衬底定位。 第一衬底可以承载第一衬底内的纳米级间距的电路组件。 第一衬底可以包括在第一衬底的表面上的微结构焊盘。 通孔可以将微型接合焊盘之一电连接到电路部件之一。 第二衬底可以电连接到至少一个微结构焊盘。

公开(公告)号：US20130221419A1

公开(公告)日：2013-08-29

申请号：US13858141

申请日：2013-04-08

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade ,  Gurtej S. Sandhu

IPC: H01L27/06

CPC classification number: H01L29/7841 ,  G11C11/565 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/51 ,  G11C2213/53 ,  G11C2213/77 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/792

Abstract: A memcapacitor device includes a pair of opposing conductive electrodes. A semiconductive material including mobile dopants within a dielectric and a mobile dopant barrier dielectric material are received between the pair of opposing conductive electrodes. The semiconductive material and the barrier dielectric material are of different composition relative one another which is at least characterized by at least one different atomic element. One of the semiconductive material and the barrier dielectric material is closer to one of the pair of electrodes than is the other of the semiconductive material and the barrier dielectric material. The other of the semiconductive material and the barrier dielectric material is closer to the other of the pair of electrodes than is the one of the semiconductive material and the barrier dielectric material. Other implementations are disclosed, including field effect transistors, memory arrays, and methods.

Abstract translation: 电容器装置包括一对相对的导电电极。 包括电介质中的移动掺杂剂和可移动掺杂剂阻挡介电材料的半导体材料被接收在该对相对的导电电极之间。 半导体材料和阻挡介电材料的组成彼此不同，其至少特征在于至少一种不同的原子元素。 半导体材料和阻挡介电材料之一比半导体材料和阻挡介电材料中的另一个更靠近一对电极之一。 半导体材料和阻挡介电材料中的另一个比半导体材料和阻挡介电材料中的一个更接近于该对电极中的另一个。 公开了其他实现方式，包括场效应晶体管，存储器阵列和方法。

公开(公告)号：US10796744B2

公开(公告)日：2020-10-06

申请号：US16438057

申请日：2019-06-11

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade

IPC: G11C11/24 ,  G11C8/08 ,  G11C13/00 ,  G11C11/56 ,  H01L27/10 ,  H01L49/02 ,  G11C11/34 ,  H01L45/00

Abstract: Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.

公开(公告)号：US10360967B2

公开(公告)日：2019-07-23

申请号：US15823139

申请日：2017-11-27

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade

IPC: G11C8/08 ,  G11C11/24 ,  G11C13/00 ,  G11C11/56 ,  H01L27/10 ,  H01L49/02 ,  G11C11/34 ,  H01L45/00

Abstract: Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.