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公开(公告)号：US11237580B1
公开(公告)日：2022-02-01
申请号：US17015486
申请日：2020-09-09
Applicant: QUALCOMM Incorporated
Inventor： Giby Samson , Foua Vang , Ramaprasath Vilangudipitchai , Seung Hyuk Kang , Venugopal Boynapalli
Abstract: A system includes: a first power supply; a second power supply; a headswitch disposed between the first power supply and logic circuitry; an enable driver coupling the second power supply to a control terminal of the headswitch; and a voltage generator operable to adjust a control voltage from the second power supply to the control terminal of the headswitch in response to a first voltage level of the first power supply exceeding a reference voltage level.
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公开(公告)号：US10026735B2
公开(公告)日：2018-07-17
申请号：US15360777
申请日：2016-11-23
Applicant: QUALCOMM Incorporated
Inventor： Andi Zhao , Ramaprasath Vilangudipitchai , Dorav Kumar
IPC: H01L23/522 , H01L27/088 , H01L23/528 , H01L27/02 , H03K17/16
Abstract: A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is coupled to other pMOS transistor gates. Each pMOS transistor source/drain are coupled to a first voltage source. The MOS IC further includes a first metal interconnect extending over the pMOS transistors. The first metal interconnect has first and second ends. The first metal interconnect is coupled to each pMOS transistor gate and is coupled to a second voltage source less than the first voltage source. One of each pMOS transistor gate or the second voltage source is coupled to the first metal interconnect through at least one tap point located between the first and second ends. The pMOS transistors and the first metal interconnect function as a decoupling capacitor.
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公开(公告)号：US09665160B1
公开(公告)日：2017-05-30
申请号：US15156859
申请日：2016-05-17
Applicant: QUALCOMM Incorporated
Inventor： Lipeng Cao , Divjyot Bhan , Harshat Pant , Ramaprasath Vilangudipitchai
IPC: H03K3/356 , G06F1/32 , H03K3/3562 , H03K5/08 , G06F13/364
CPC classification number: G06F1/324 , G06F1/3287 , G06F13/364 , H03K3/0372 , H03K3/0375 , H03K3/3562 , H03K5/08 , Y02D10/171
Abstract: An integrated circuit (IC) is disclosed having a unified control scheme and a unifying architecture for different types of retention flip-flops (RFFs). In an example aspect, an IC includes a constant power rail to provide power during a power collapse period and a collapsible power rail to cease providing power during the power collapse period. The IC also includes a positive-edge-triggered (PET) RFF and a negative-edge-triggered (NET) RFF. The PET RFF includes a master portion and a slave portion, with the slave portion coupled to the constant power rail and the master portion coupled to the collapsible power rail. The NET RFF includes master and slave portions, with the master portion coupled to the constant power rail and the slave portion coupled to the collapsible power rail. In another example aspect, a control signal based on a clock and a retention signal may be routed to both RFFs.
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24.发明授权公开(公告)号：US09634026B1
公开(公告)日：2017-04-25
申请号：US15209650
申请日：2016-07-13
Applicant: QUALCOMM Incorporated
Inventor： Satyanarayana Sahu , Xiangdong Chen , Ramaprasath Vilangudipitchai , Dorav Kumar
IPC: H03K19/00 , H01L27/11 , H01L27/118 , H03K19/003 , H01L27/02 , H01L27/092 , H03K19/177
CPC classification number: H01L27/11807 , H01L27/0207 , H01L27/0266 , H01L27/092 , H01L28/00 , H01L2027/11875 , H03K19/0008 , H03K19/00361 , H03K19/17728 , H03K19/17736
Abstract: A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.
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公开(公告)号：US20140306735A1
公开(公告)日：2014-10-16
申请号：US13862015
申请日：2013-04-12
Applicant: QUALCOMM INCORPORATED
Inventor： Seid Hadi Rasouli , Animesh Datta , Jay Madhukar Shah , Martin Saint-Laurent , Peeyush Kumar Parkar , Sachin Bapat , Ramaprasath Vilangudipitchai , Mohamed Hassan Abu-Rahma , Prayag Bhanubhai Patel
IPC: H03K3/012
CPC classification number: H03K3/012 , H03K3/356008 , H03K3/35625
Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.
Abstract translation: 包括响应于时钟信号和控制信号的逻辑门的电路。 电路还包括触发器的主级。 电路还包括响应于主级的触发器的从级。 电路还包括响应逻辑门并被配置为输出时钟信号的延迟版本的反相器。 逻辑门的输出和时钟信号的延迟版本被提供给主级和触发器的从级。 主级响应控制信号来控制从机级。
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Patent Agency Ranking
公开(公告)号：US10103626B1
公开(公告)日：2018-10-16
申请号：US15647326
申请日：2017-07-12
Applicant: QUALCOMM Incorporated
Inventor： Venkatasubramanian Narayanan , Dorav Kumar , Ramaprasath Vilangudipitchai , Venugopal Boynapalli
IPC: H02M3/157 , H03K17/687 , H03K19/173 , H02M3/335
Abstract: A power multiplexor includes: a first branch including a first transistor coupled in series with a second transistor between a first power supply and a power output; a second branch including a third transistor coupled in series with a fourth transistor between a second power supply and the power output; a controller configured to selectively assert and de-assert a control signal to the first branch and the second branch; a first voltage level shifter coupled between the second transistor and the controller; and a second voltage level shifter coupled between the third transistor and the controller.
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公开(公告)号：US20180006651A1
公开(公告)日：2018-01-04
申请号：US15367751
申请日：2016-12-02
Applicant: QUALCOMM Incorporated
Inventor： Venkat Narayanan , Rakesh Vattikonda , De Lu , Ramaprasath Vilangudipitchai , Samrat Sinharoy , Rui Chen
IPC: H03K19/0185 , H03K19/00
CPC classification number: H03K19/018521 , H03K3/356121 , H03K3/356191 , H03K19/0013 , H03K19/01855 , H03K19/0963
Abstract: In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.
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公开(公告)号：US09852859B2
公开(公告)日：2017-12-26
申请号：US14981183
申请日：2015-12-28
Applicant: QUALCOMM Incorporated
Inventor： Lipeng Cao , Dorav Kumar , Bilal Zafar , Ramaprasath Vilangudipitchai , Venkatasubramanian Narayanan , Xi Luo
CPC classification number: H01H47/00 , H03K19/0008
Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.
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公开(公告)号：US20170186576A1
公开(公告)日：2017-06-29
申请号：US14981183
申请日：2015-12-28
Applicant: QUALCOMM Incorporated
Inventor： Lipeng Cao , Dorav Kumar , Bilal Zafar , Ramaprasath Vilangudipitchai , Venkatasubramanian Narayanan , Xi Luo
IPC: H01H47/00
CPC classification number: H01H47/00 , H03K19/0008
Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.
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公开(公告)号：US09673786B2
公开(公告)日：2017-06-06
申请号：US13862015
申请日：2013-04-12
Applicant: QUALCOMM Incorporated
Inventor： Seid Hadi Rasouli , Animesh Datta , Jay Madhukar Shah , Martin Saint-Laurent , Peeyush Kumar Parkar , Sachin Bapat , Ramaprasath Vilangudipitchai , Mohamed Hassan Abu-Rahma , Prayag Bhanubhai Patel
CPC classification number: H03K3/012 , H03K3/356008 , H03K3/35625
Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.
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