公开(公告)号：US20170179261A1

公开(公告)日：2017-06-22

申请号：US15448099

申请日：2017-03-02

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Xia Li

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/02 ,  H01L27/11568 ,  H01L21/324 ,  H01L21/28

CPC classification number: H01L29/66833 ,  G11C11/221 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/28185 ,  H01L21/324 ,  H01L27/088 ,  H01L27/11568 ,  H01L27/11592 ,  H01L29/40111 ,  H01L29/40117 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78 ,  H01L29/785

Abstract: A method of forming an electronic device includes forming an oxygen scavenging layer proximate to a dielectric layer in a gate region of a field effect transistor (FET). The interface layer is between the dielectric layer and a substrate of the FET. The method further includes forming a dipole layer by annealing the oxygen scavenging layer, the dielectric layer, and the interface layer.

公开(公告)号：US09679663B2

公开(公告)日：2017-06-13

申请号：US14994231

申请日：2016-01-13

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Kangho Lee ,  Seung H. Kang ,  Xia Li ,  Wah Nam Hsu

IPC: G11C11/00 ,  G11C17/18 ,  G11C11/16 ,  G11C17/02 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C17/165

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

公开(公告)号：US09576801B2

公开(公告)日：2017-02-21

申请号：US14556983

申请日：2014-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Zhongze Wang ,  Bin Yang ,  Xiaonan Chen ,  Yu Lu

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L21/02 ,  G11C16/04

CPC classification number: H01L21/28088 ,  G11C16/0408 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/7883

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a nonvolatile memory device.

Abstract translation: 使用与高介电常数/金属栅（HK / MG）工艺兼容的工艺制造非易失性存储器件和逻辑器件，用于增加电池密度和更大规模的集成。 掺杂氧化物层，例如掺杂硅的氧化铪（HfO 2）层，在非易失性存储器件中被实现为铁电偶极子层。

公开(公告)号：US09548333B2

公开(公告)日：2017-01-17

申请号：US14496525

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L27/22 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L45/02 ,  H01L45/00 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L27/222 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L43/08 ,  H01L43/12 ,  H01L45/02 ,  H01L45/08 ,  H01L45/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods of integration of resistive memory elements with logic elements in advanced nodes with improved mechanical stability and reduced parasitic capacitance include a resistive memory element and a logic element formed in a common integration layer extending between a bottom cap layer and a top cap layer. At least a first intermetal dielectric (IMD) layer of high-K value is formed in the common integration layer and surrounding at least the resistive memory element, to provide high rigidity and mechanical stability. A second IMD layer of low-K value to reduce parasitic capacitance of the logic element is formed in either the common integration layer, a top layer above the top cap layer or an intermediate layer in between the top and bottom cap layers. Air gaps may be formed in one or more IMD layers to further reduce capacitance.

Abstract translation: 电阻式存储器元件与具有改进的机械稳定性和减小的寄生电容的先进节点中的逻辑元件的集成的系统和方法包括形成在底盖层和顶盖层之间延伸的公共集成层中的电阻存储元件和逻辑元件。 至少在公共积分层中形成高K值的第一金属间电介质（IMD）层，并且至少围绕电阻式存储元件，以提供高刚性和机械稳定性。 降低逻辑元件的寄生电容的低K值的第二IMD层形成在公共集成层，顶盖层上的顶层或顶盖层之间的中间层。 可以在一个或多个IMD层中形成气隙，以进一步降低电容。

公开(公告)号：US20160268256A1

公开(公告)日：2016-09-15

申请号：US14657021

申请日：2015-03-13

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Jun Yuan

IPC: H01L27/088 ,  H01L29/161 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823487 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/7827 ,  H01L29/7848 ,  H01L29/7851

Abstract: An apparatus includes a structure that includes a single substrate, a planar complementary metal-oxide semiconductor (CMOS) transistor formed on the single substrate, a planar tunnel field-effect transistor (TFET) formed on the single substrate, and a mobility enhancement strength layer included in the planar CMOS transistor or included in the planar TFET.

Abstract translation: 一种装置包括一种结构，其包括单个衬底，形成在单个衬底上的平面互补金属氧化物半导体（CMOS）晶体管，形成在单个衬底上的平面隧道场效应晶体管（TFET）和迁移率增强强度层 包括在平面CMOS晶体管中或包括在平面TFET中。

公开(公告)号：US20160248002A1

公开(公告)日：2016-08-25

申请号：US14630438

申请日：2015-02-24

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Junjing Bao ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/16 ,  H01L23/544 ,  H01L43/08 ,  H01L43/12 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A semiconductor device includes an interconnect layer and a bottom electrode of a resistive memory device. The bottom electrode is coupled to the interconnect layer, and the bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).

Abstract translation: 半导体器件包括电阻式存储器件的互连层和底部电极。 底部电极耦合到互连层，底部电极由钴钨磷（CoWP）组成。

公开(公告)号：US09425296B2

公开(公告)日：2016-08-23

申请号：US14021795

申请日：2013-09-09

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Ming Cai ,  Bin Yang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/66977 ,  H01L29/66356 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7827

Abstract: A tunnel field transistor (TFET) device includes a fin structure that protrudes from a substrate surface. The fin structure includes a base portion proximate to the substrate surface, a top portion, and a first pair of sidewalls extending from the base portion to the top portion. The first pair of sidewalls has a length corresponding to a length of the fin structure. The fin structure also includes a first doped region having a first dopant concentration at the base portion of the fin structure. The fin structure also includes a second doped region having a second dopant concentration at the top portion of the fin structure. The TFET device further includes a gate including a first conductive structure neighboring a first sidewall of the first pair of sidewalls. A dielectric layer electrically isolates the first conductive structure from the first sidewall.

Abstract translation: 隧道场晶体管（TFET）器件包括从衬底表面突出的鳍结构。 翅片结构包括靠近基底表面的基部，顶部和从基部延伸到顶部的第一对侧壁。 第一对侧壁的长度对应于翅片结构的长度。 翅片结构还包括在鳍结构的基部处具有第一掺杂剂浓度的第一掺杂区域。 鳍结构还包括在鳍结构的顶部具有第二掺杂剂浓度的第二掺杂区。 TFET器件还包括栅极，其包括与第一对侧壁的第一侧壁相邻的第一导电结构。 电介质层将第一导电结构与第一侧壁电隔离。

公开(公告)号：US09413349B1

公开(公告)日：2016-08-09

申请号：US14676228

申请日：2015-04-01

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiao Lu ,  Xiaonan Chen ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C16/10 ,  H03K17/687 ,  H01L29/792 ,  H01L29/51 ,  H01L27/115 ,  G11C16/04

CPC classification number: H03K17/687 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/1052 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/792

Abstract: Aspects disclosed in the detailed description include high-k (HK)/metal gate (MG) (HK/MG) multi-time programmable (MTP) switching devices, and related systems and methods. One type of HK/MG MTP switching device is an MTP metal-oxide semiconductor (MOS) field-effect transistor (MOSFET). When the MTP MOSFET is programmed, a charge trap may build up in the MTP MOSFET due to a switching electrical current induced by a switching voltage. The charge trap reduces the switching window and endurance of the MTP MOSFET, thus reducing reliability in accessing the information stored in the MTP MOSFET. In this regard, an HK/MG MTP switching device comprising the MTP MOSFET is configured to eliminate the switching electrical current when the MTP MOSFET is programmed. By eliminating the switching electrical current, it is possible to avoid a charge trap in the MTP MOSFET, thus restoring the switching window and endurance of the MTP MOSFET for reliable information access.

Abstract translation: 在详细描述中公开的方面包括高k（HK）/金属门（MG）（HK / MG）多时间可编程（MTP）交换设备以及相关的系统和方法。 一种类型的HK / MG MTP开关器件是MTP金属氧化物半导体（MOS）场效应晶体管（MOSFET）。 当编程MTP MOSFET时，由于开关电压引起的开关电流，电荷陷阱可能会积累在MTP MOSFET中。 电荷阱减少了MTP MOSFET的开关窗口和耐久性，从而降低了访问存储在MTP MOSFET中的信息的可靠性。 在这方面，包括MTP MOSFET的HK / MG MTP开关器件被配置为在编程MTP MOSFET时消除开关电流。 通过消除开关电流，可以避免MTP MOSFET中的电荷陷阱，从而恢复MTP MOSFET的开关窗口和耐用性，从而实现可靠的信息访问。

公开(公告)号：US09406689B2

公开(公告)日：2016-08-02

申请号：US14044725

申请日：2013-10-02

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Seung Hyuk Kang

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7883 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: A method for fabricating a multiple time programmable (MTP) device includes forming fins of a first conducting type on a substrate of a second conducting type. The method further includes forming a floating gate dielectric to partially surround the fins. The method also includes forming a floating gate on the floating gate dielectric. The method also includes forming a coupling film on the floating gate and forming a coupling gate on the coupling film.

Abstract translation: 一种制造多时间可编程（MTP）器件的方法包括在第二导电类型的衬底上形成第一导电类型的鳍片。 该方法还包括形成浮动栅极电介质以部分地围绕鳍片。 该方法还包括在浮栅电介质上形成浮栅。 该方法还包括在浮栅上形成耦合膜并在耦合膜上形成耦合栅极。

公开(公告)号：US09318696B2

公开(公告)日：2016-04-19

申请号：US14195566

申请日：2014-03-03

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xia Li ,  Seung Hyuk Kang ,  Shiqun Gu

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L21/76802 ,  H01L21/76813 ,  H01L21/76832 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: Systems and methods for forming precise and self-aligned top metal contact for a Magnetoresistive random-access memory (MRAM) device include forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with a logic element. A low dielectric constant (K) etch stop layer is selectively retained over an exposed top surface of the MTJ. Etching is selectively performed through a top IMD layer formed over the low K etch stop layer and the common IMD layer, based on a first chemistry which prevents etching through the low K etch stop layer. By switching chemistry to a second chemistry which precisely etches through the low K etch stop layer, an opening is created for forming a self-aligned top contact to the exposed top surface of the MTJ.

Abstract translation: 用于形成用于磁阻随机存取存储器（MRAM）器件的精确和自对准的顶部金属接触的系统和方法包括在具有逻辑元件的公共层间金属电介质（IMD）层中形成磁性隧道结（MTJ）。 低介电常数（K）蚀刻停止层选择性地保留在MTJ的暴露的顶表面上。 基于防止蚀刻通过低K蚀刻停止层的第一化学反应，通过形成在低K蚀刻停止层和公共IMD层上的顶部IMD层选择性地进行蚀刻。 通过将化学转换成精确地蚀刻通过低K蚀刻停止层的第二化学物质，形成一个开口以形成与MTJ暴露的顶表面的自对准顶部接触。