公开(公告)号：US20070273023A1

公开(公告)日：2007-11-29

申请号：US11583718

申请日：2006-10-20

Applicant: Sam Ziqun Zhao ,  Edward Law ,  Rezaur Rahman Khan

Inventor： Sam Ziqun Zhao ,  Edward Law ,  Rezaur Rahman Khan

IPC: H01L23/34

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus and method for a wire-bond die-up area array package is described. The package includes an integrated circuit (IC) die, a substrate, and a thermally conducting body. A bottom surface of the IC die is exposed through an opening in a central region of the substrate. The die is mounted to the thermally conducting body. A bottom surface of the thermally conducting body is configured to be connected to a circuit board, such as a PWB, when the package is mounted to the circuit board. The bottom surface of the thermally conducting body may be connected directly to the circuit board, or may be coupled to the circuit board via solder balls or other mechanism. One or more wirebonds are used to electrically connect the die to a top surface of the substrate. A mold compound encapsulates the die, the wirebonds, and at least a portion of the top surface of the substrate, and fills a gap between peripheral edges of the IC die and inner walls of the substrate central window opening. A matrix of solder balls is attached to a bottom surface of the substrate.

Abstract translation: 描述了一种用于引线键合区域阵列封装的装置和方法。 封装包括集成电路（IC）管芯，衬底和导热体。 IC芯片的底表面通过衬底的中心区域中的开口露出。 模具安装到导热体上。 当封装安装到电路板时，导热体的底表面被配置为连接到电路板，例如PWB。 导热体的底表面可以直接连接到电路板，或者可以通过焊球或其它机构与电路板耦合。 一个或多个引线用于将管芯电连接到衬底的顶表面。 模具化合物封装模具，引线键和衬底的顶表面的至少一部分，并且填充IC模具的周边边缘和衬底中心窗口的内壁之间的间隙。 焊球的基体附着在基板的底面上。

公开(公告)号：US07161239B2

公开(公告)日：2007-01-09

申请号：US10284312

申请日：2002-10-31

Applicant: Sam Ziqun Zhao ,  Reza-ur Rahman Khan

Inventor： Sam Ziqun Zhao ,  Reza-ur Rahman Khan

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L23/3735 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49833 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/0204 ,  H05K1/182 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. A substrate has a surface, wherein the surface has an opening therein. A stiffener has a surface coupled to the surface of the substrate. An area of the surface of the stiffener can be greater than, equal to, or less than an area of the surface of the substrate. A thermal connector is coupled to the surface of the stiffener through the opening. A surface of the thermal connector is capable of attachment to a printed circuit board (PCB) when the BGA package is mounted to the PCB. The thermal connector can have a height such that the thermal connector extends into a cavity formed in a surface of the PCB when the BGA package is mounted to the PCB. Alternatively, the stiffener and thermal connector may be combined into a single piece stiffener, wherein the stiffener has a protruding portion. The protruding portion extends through the opening when the stiffener is coupled to the substrate, and is capable of attachment to the PCB.

Abstract translation: 描述了电，机械和热增强球栅阵列（BGA）封装。 衬底具有表面，其中表面在其中具有开口。 加强件具有连接到基底表面的表面。 加强件的表面的面积可以大于，等于或小于衬底表面的面积。 热连接器通过开口连接到加强件的表面。 当BGA封装安装到PCB时，热连接器的表面能够连接到印刷电路板（PCB）。 热连接器可以具有这样的高度，使得当BGA封装安装到PCB时，热连接器延伸到形成在PCB的表面中的空腔中。 或者，加强件和热连接器可以组合成单件加强件，其中加强件具有突出部分。 当加强件联接到基板上时，突出部分延伸穿过开口，并且能够附接到PCB。

公开(公告)号：US09153507B2

公开(公告)日：2015-10-06

申请号：US13362344

申请日：2012-01-31

Applicant: Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

Inventor： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC: G01R31/02 ,  H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2224/81 ,  H01L2924/014

Abstract: An exemplary implementation of the present disclosure includes a testable semiconductor package that includes an active die having interface contacts and dedicated testing contacts. An interposer is situated adjacent a bottom surface of the active die, the interposer providing electrical connections between the interface contacts and a bottom surface of the testable semiconductor package. At least one conductive medium provides electrical connection between at least one of the dedicated testing contacts and a top surface of the testable semiconductor package. The at least one conductive medium can be coupled to a package-top testing connection, which may include a solder ball.

Abstract translation: 本公开的示例性实现包括可测试的半导体封装，其包括具有接口触点和专用测试触点的有源裸片。 插入器位于有源裸片的底表面附近，插入器提供接口触点之间的电连接和可测试的半导体封装的底表面。 至少一个导电介质提供至少一个专用测试触点和可测半导体封装的顶表面之间的电连接。 所述至少一个导电介质可以耦合到封装顶部测试连接，其可以包括焊球。

公开(公告)号：US08791533B2

公开(公告)日：2014-07-29

申请号：US13361598

申请日：2012-01-30

Applicant: Xiangdong Chen ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

Inventor： Xiangdong Chen ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

IPC: H01L29/82

CPC classification number: H01L23/48 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2225/06531 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There are disclosed herein various implementations of semiconductor packages having an interposer configured for magnetic signaling. One exemplary implementation includes a die transmit pad in an active die for transmitting a magnetic signal corresponding to a die electrical signal produced by the active die, and an interposer magnetic tunnel junction (MTJ) pad in the interposer for receiving the magnetic signal. A sensing circuit is coupled to the interposer MTJ pad for producing a receive electrical signal corresponding to the magnetic signal. In one implementation, the sensing circuit is configured to sense a resistance of the interposer MTJ pad and to produce the receive electrical signal according to the sensed resistance.

Abstract translation: 这里公开了具有配置用于磁信令的插入器的半导体封装的各种实施方式。 一个示例性实施例包括用于传输对应于由有源管芯产生的管芯电信号的磁信号的有源管芯中的管芯发射焊盘以及用于接收磁信号的插入器磁隧道结（MTJ）焊盘。 感测电路耦合到插入器MTJ焊盘，用于产生对应于磁信号的接收电信号。 在一个实现中，感测电路被配置为感测插入器MTJ焊盘的电阻并且根据所感测的电阻产生接收电信号。

公开(公告)号：US20140061893A1

公开(公告)日：2014-03-06

申请号：US13598291

申请日：2012-08-29

Applicant: Seyed Mahdi Saeidi ,  Sam Ziqun Zhao

Inventor： Seyed Mahdi Saeidi ,  Sam Ziqun Zhao

IPC: H01L23/34 ,  H01L21/50

CPC classification number: H01L23/3675 ,  H01L21/52 ,  H01L23/16 ,  H01L23/42 ,  H01L23/562 ,  H01L24/33 ,  H01L2224/16225 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/29076 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33051 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.

Abstract translation: 描述了包括两个或更多个热界面材料（TIM）的翻转芯片封装。 通过焊料凸块将裸片安装到基板上。 第一个TIM应用于管芯，并具有第一个热阻。 第二TIM施加到管芯和/或衬底，并且具有大于第一热阻的第二热阻。 散热器盖的开口端安装到基板上，使得模具定位在由散热器盖和基板形成的外壳中。 第一TIM和第二TIM分别与散热器盖的内表面接触。 环形加强件可以围绕模具并且通过第二TIM连接在基板和散热器盖之间。

公开(公告)号：US20130214410A1

公开(公告)日：2013-08-22

申请号：US13401457

申请日：2012-02-21

Applicant: Rezaur Rahman Khan ,  Sam Ziqun Zhao

Inventor： Rezaur Rahman Khan ,  Sam Ziqun Zhao

IPC: H01L23/48 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L23/12 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Abstract translation: 公开了一种界面衬底，其包括具有贯通半导体通孔的插入件。 进一步围绕插入件构建上部和下部有机衬底。 所公开的接口衬底能够持续使用低成本且广泛部署的用于半导体封装的有机衬底，同时提供若干优点。 将有机基底分离成上下基板能够实现制造设备的成本有效匹配。 通过在一个有机衬底中设置一个开口，一个或多个半导体管芯可以附着到与插入器的通孔半导体连接的暴露的互连焊盘上，使得能够使用具有高密度微型阵列的倒装芯片和模具 具有不同的凸起间距。 通过在上部有机衬底中提供开口，还可以提供具有优化的高度的封装封装结构。

公开(公告)号：US20130193996A1

公开(公告)日：2013-08-01

申请号：US13362344

申请日：2012-01-31

Applicant: Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

Inventor： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC: G01R31/26 ,  H01L23/544

CPC classification number: H01L22/32 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2224/81 ,  H01L2924/014

Abstract: An exemplary implementation of the present disclosure includes a testable semiconductor package that includes an active die having interface contacts and dedicated testing contacts. An interposer is situated adjacent a bottom surface of the active die, the interposer providing electrical connections between the interface contacts and a bottom surface of the testable semiconductor package. At least one conductive medium provides electrical connection between at least one of the dedicated testing contacts and a top surface of the testable semiconductor package. The at least one conductive medium can be coupled to a package-top testing connection, which may include a solder ball.

Abstract translation: 本公开的示例性实现包括可测试的半导体封装，其包括具有接口触点和专用测试触点的有源裸片。 插入器位于有源裸片的底表面附近，插入器提供接口触点之间的电连接和可测试的半导体封装的底表面。 至少一个导电介质提供至少一个专用测试触点和可测半导体封装的顶表面之间的电连接。 所述至少一个导电介质可以耦合到封装顶部测试连接，其可以包括焊球。

公开(公告)号：US20130193587A1

公开(公告)日：2013-08-01

申请号：US13361598

申请日：2012-01-30

Applicant: Xiangdong Chen ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

Inventor： Xiangdong Chen ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

IPC: H01L23/52

CPC classification number: H01L23/48 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2225/06531 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There are disclosed herein various implementations of semiconductor packages having an interposer configured for magnetic signaling. One exemplary implementation includes a die transmit pad in an active die for transmitting a magnetic signal corresponding to a die electrical signal produced by the active die, and an interposer magnetic tunnel junction (MTJ) pad in the interposer for receiving the magnetic signal. A sensing circuit is coupled to the interposer MTJ pad for producing a receive electrical signal corresponding to the magnetic signal. In one implementation, the sensing circuit is configured to sense a resistance of the interposer MTJ pad and to produce the receive electrical signal according to the sensed resistance.

Abstract translation: 这里公开了具有配置用于磁信令的插入器的半导体封装的各种实施方式。 一个示例性实施例包括用于传输对应于由有源管芯产生的管芯电信号的磁信号的有源管芯中的管芯发射焊盘，以及用于接收磁信号的插入器磁隧道结（MTJ）焊盘。 感测电路耦合到插入器MTJ焊盘，用于产生对应于磁信号的接收电信号。 在一个实现中，感测电路被配置为感测插入器MTJ焊盘的电阻并且根据所感测的电阻产生接收电信号。

公开(公告)号：US20130168860A1

公开(公告)日：2013-07-04

申请号：US13339234

申请日：2011-12-28

Applicant: Sampath K.V. Karikalan ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

Inventor： Sampath K.V. Karikalan ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC: H01L23/538 ,  H01L23/532

CPC classification number: H01L23/538 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5223 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: There are disclosed herein various implementations of semiconductor packages including an interposer without through-semiconductor vias (TSVs). One exemplary implementation includes a first active die situated over an interposer. The interposer includes an interposer dielectric having intra-interposer routing traces. The first active die communicates electrical signals to a package substrate situated below the interposer utilizing the intra-interposer routing traces and without utilizing TSVs. In one implementation, the semiconductor package includes a second active die situated over the interposer, the second active die communicating electrical signals to the package substrate utilizing the intra-interposer routing traces and without utilizing TSVs. Moreover, in one implementation, the first active die and the second active die communicate chip-to-chip signals through the interposer.

Abstract translation: 这里公开了包括没有半导体通孔（TSV）的插入器的半导体封装的各种实施方式。 一个示例性实施方式包括位于中介层之上的第一有源裸片。 插入器包括具有内插器布线迹线的中介层电介质。 第一有源管芯将电信号传送到位于插入器下方的封装衬底，利用内插器布线迹线并且不使用TSV。 在一个实施方案中，半导体封装包括位于插入器上方的第二有源裸片，第二有源裸片利用内插器布线迹线将电信号传送到封装衬底，并且不使用TSV。 此外，在一个实现中，第一有源管芯和第二有源管芯通过插入器传送芯片到芯片信号。

公开(公告)号：US20130168841A1

公开(公告)日：2013-07-04

申请号：US13340430

申请日：2011-12-29

Applicant: Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

Inventor： Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Sampath K.V. Karikalan ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC: H01L23/495 ,  H01L21/326 ,  H05K1/11 ,  B82Y99/00

CPC classification number: H01L23/49827 ,  B82Y10/00 ,  H01L21/485 ,  H01L21/486 ,  H01L23/49822 ,  H01L2224/16225 ,  H05K1/029 ,  H05K3/4038 ,  H05K2201/0248 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/10378 ,  H05K2203/104 ,  H05K2203/105

Abstract: An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.

Abstract translation: 本公开的示例性实现包括具有顶部和底部接口电极和散布在可编程插值器内的导电粒子的可编程插值器。 响应于将能量场施加到可编程内插器，导电颗粒能够在顶部和底部界面电极之间形成对准的构造，以便电连接顶部和底部界面电极。 导电颗粒可具有导电外表面。 此外，导电粒子可以是球形的。 导电颗粒可以在可编程插入器中的界面层中的体积材料内，并且可以固化块状材料以确保顶部和底部界面电极之间的编程路径。