公开(公告)号：US09397020B2

公开(公告)日：2016-07-19

申请号：US14455849

申请日：2014-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Woo Park

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/13 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L23/13 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor package includes a substrate including a lower plate and an upper plate, a semiconductor chip mounted on a top surface of the substrate, and a mold layer surrounding a sidewall and a bottom surface of the semiconductor chip. The substrate has a mold path including an inner path extending between the lower and upper plates and a mold hole penetrating the upper plate. The mold hole is connected to the inner path. The mold layer extends into the mold path.

Abstract translation: 半导体封装包括：包括下板和上板的衬底;安装在衬底顶表面上的半导体芯片;以及围绕半导体芯片的侧壁和底表面的模制层。 基板具有包括在下板和上板之间延伸的内部通道的模具路径和穿过上板的模具孔。 模具孔连接到内部路径。 模具层延伸到模具路径中。

公开(公告)号：US09087883B2

公开(公告)日：2015-07-21

申请号：US14464014

申请日：2014-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeokHyun Lee ,  Jin-Woo Park ,  Taesung Park

IPC: H01L21/50 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L21/82 ,  H01L21/56

CPC classification number: H01L21/76892 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76822 ,  H01L21/76894 ,  H01L21/82 ,  H01L23/3185 ,  H01L23/48 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/821 ,  H01L2224/82365 ,  H01L2224/95 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/01029 ,  H05K3/4661 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00

Abstract: Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip.

Abstract translation: 堆叠的半导体芯片包括将半导体芯片电连接到每个芯片的无接线的互连。 在半导体芯片之间的粘合层中的开口可以提供用于从沿着半导体芯片的侧壁绝缘层的一个半导体芯片上的接合焊盘沿另一个半导体芯片的侧壁绝缘层到接合焊盘的互连的路径 另一个半导体芯片。

公开(公告)号：US20240055398A1

公开(公告)日：2024-02-15

申请号：US18309250

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong Bin Yim ,  Ji-Yong Park ,  Jin-Woo Park ,  Jong Bo Shim

IPC: H01L25/065 ,  H10B80/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H10B80/00 ,  H01L23/3107 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32137 ,  H01L2224/32245 ,  H01L2224/32225 ,  H01L2224/33051 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73215 ,  H01L2924/1431 ,  H01L2924/1443 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441

Abstract: A semiconductor package includes a first substrate, a memory semiconductor package on a first surface of the first substrate, an adhesive layer between the first surface of the first substrate and the memory semiconductor package, a wire extending from an upper surface of the memory semiconductor package and connected to the first substrate, a logic semiconductor chip on the first surface of the first substrate, a first connection terminal between the first surface of the first substrate and the logic semiconductor chip, and a molding layer, wherein a first height of the memory semiconductor package is smaller than a second height of the logic semiconductor chip, and wherein an uppermost surface of the molding layer and the upper surface of the logic semiconductor chip are coplanar.

公开(公告)号：US10355429B2

公开(公告)日：2019-07-16

申请号：US15657006

申请日：2017-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  HYUPJINCONNECTOR CO., LTD.

Inventor： Myeong-Hwa Kim ,  Yang-Jean Park ,  Yeon-Kwan Moon ,  Jin-Woo Park ,  Myung-Suk Bae ,  Jung-Hyun Cho ,  Jin-Hyuk Choi ,  Jae-Ryong Han ,  Jang-Won Hur

IPC: H01R13/73 ,  H01R13/74 ,  H01R12/71 ,  H01R13/24

Abstract: A connection terminal device and an electronic device having the same are provided. The connection terminal device includes a connection terminal device body, and a connection terminal connected to the connection terminal device body. The connection terminal device also has a front unit disposed on a front surface of the connection terminal device body, a rear unit disposed on a rear surface of the connection terminal device body, and a support disposed on the rear surface of the connection terminal device body. When force is applied to the connection terminal, supporting force is transferred to the rear unit of the connection terminal device body.

公开(公告)号：US10338238B2

公开(公告)日：2019-07-02

申请号：US14953051

申请日：2015-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Ik Kim ,  Jin-Woo Park ,  Eun Jeong Jo

IPC: G01T7/00 ,  A61B6/00

Abstract: Disclosed herein are an X-ray detector, in which an active area of the X-ray detector has an improved structure for a user's convenience, and an X-ray imaging apparatus having the same, The X-ray detector is configured to detect X-rays irradiated from an X-ray source, and includes: a top frame that includes a first area, a second area which is bent from the first area, and an active area which is biased from a center of the first area; a side frame that includes a top frame resting part which is formed in an outer surface which faces an outside of the X-ray detector and on which the second area rests, the side frame being coupled with the top frame to form an accommodation space; and a sensor panel disposed in the accommodation space and configured to convert the detected X-rays into an electrical signal, the sensor panel being biased from the center of the first area to correspond to the active area.

公开(公告)号：US20190156896A1

公开(公告)日：2019-05-23

申请号：US16043964

申请日：2018-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Yoon Park ,  Wan-Dong Kim ,  Seung-Bum Kim ,  Deok-Woo Lee ,  You-Se Kim ,  Se-Hwan Park ,  Jin-Woo Park

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/3445 ,  G11C29/52

Abstract: A method of erasing a memory device, the method of erasing the memory device including: performing, in a first erase period, a first erase operation on memory cells respectively connected to a plurality of word lines, wherein at least one of the memory cells, which is included in a memory block, is not erase-passed; determining, after the first erase period, an erase operation speed by applying a verify voltage to at least one of the plurality of word lines, and determining an effective erasing time for each word line based on the determined erase operation speed; and performing, in a second erase period, a second erase operation on the memory cells respectively connected to the plurality of word lines based on the determined effective erasing times.

公开(公告)号：US09960193B2

公开(公告)日：2018-05-01

申请号：US15136075

申请日：2016-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Woo Park ,  Siwoo Kim

IPC: H01L21/44 ,  H01L27/12 ,  G03F1/00

CPC classification number: H01L27/124 ,  G03F1/00

Abstract: A display driver integrated circuit and a method of manufacturing the same are provided. The method of manufacturing a display driver integrated circuit (DDI) including a first area, a second area, and an overlapping area in which the first area and the second area overlap each other includes forming a first pattern in the first area using a first reticle; and forming a second pattern in the second area using a second reticle, and ends of the first pattern and the second pattern are connected within the overlapping area and the first area and the second area are asymmetrically set based on the overlapping area such that the overlapping area includes only a metal line.

公开(公告)号：US09202716B2

公开(公告)日：2015-12-01

申请号：US13626012

申请日：2012-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Woo Park ,  Hogeon Song ,  Seokhyun Lee

IPC: H01L23/34 ,  H01L21/56 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/12 ,  H01L23/057 ,  H01L23/055 ,  H01L23/24 ,  H01L23/053 ,  H01L23/02 ,  H01L23/04 ,  H01L23/495 ,  H01L23/08 ,  H01L23/492 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/02 ,  H01L23/04 ,  H01L23/053 ,  H01L23/055 ,  H01L23/057 ,  H01L23/08 ,  H01L23/12 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/4926 ,  H01L23/49575 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82101 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A fan-out wafer level package may include at least two semiconductor chips; an insulating layer covering portions of a first semiconductor chip; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chip may be stacked relative to the second semiconductor chip. The redistribution line pattern may be electrically connected to the at least two semiconductor chips. The external terminal may be electrically connected to the redistribution line pattern. A fan-out wafer level package may include at least three semiconductor chips; an insulating layer covering portions of first semiconductor chips; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chips may be stacked relative to the second semiconductor chip.

Abstract translation: 扇出晶片级封装可以包括至少两个半导体芯片; 覆盖第一半导体芯片的部分的绝缘层; 覆盖第二半导体芯片的部分的模具层; 绝缘层中的再分布线图案; 和/或绝缘层上的外部端子。 第一半导体芯片可以相对于第二半导体芯片堆叠。 再分布线图案可以电连接到至少两个半导体芯片。 外部端子可以电连接到再分配线图案。 扇出晶片级封装可以包括至少三个半导体芯片; 覆盖第一半导体芯片的部分的绝缘层; 覆盖第二半导体芯片的部分的模具层; 绝缘层中的再分布线图案; 和/或绝缘层上的外部端子。 第一半导体芯片可以相对于第二半导体芯片堆叠。

公开(公告)号：US20140008818A1

公开(公告)日：2014-01-09

申请号：US13886758

申请日：2013-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeokHyun Lee ,  Jin-Woo Park ,  Taesung Park

IPC: H01L23/48

CPC classification number: H01L21/76892 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76822 ,  H01L21/76894 ,  H01L21/82 ,  H01L23/3185 ,  H01L23/48 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/821 ,  H01L2224/82365 ,  H01L2224/95 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/01029 ,  H05K3/4661 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00

Abstract: Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip.

Abstract translation: 堆叠的半导体芯片包括将半导体芯片电连接到每个芯片的无接线的互连。 在半导体芯片之间的粘合层中的开口可以提供用于从沿着半导体芯片的侧壁绝缘层的一个半导体芯片上的接合焊盘沿另一个半导体芯片的侧壁绝缘层到接合焊盘的互连的路径 另一个半导体芯片。

公开(公告)号：US12211806B2

公开(公告)日：2025-01-28

申请号：US18301606

申请日：2023-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Woo Park ,  Un-Byoung Kang ,  Jong Ho Lee

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/485 ,  H01L23/538

Abstract: A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.