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    SEMICONDUCTOR DEVICE
    22.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180090499A1

    公开(公告)日：2018-03-29

    申请号：US15722016

    申请日：2017-10-02

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi KATO

    IPC: H01L27/105

    CPC classification number: H01L27/1052 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/0688 ,  H01L27/10805 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203

    Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

    Semiconductor Device, Circuit Board, and Electronic Device
    25.
    发明申请
    Semiconductor Device, Circuit Board, and Electronic Device 有权
    半导体器件，电路板和电子器件

    公开(公告)号：US20170033111A1

    公开(公告)日：2017-02-02

    申请号：US15220706

    申请日：2016-07-27

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Hidekazu MIYAIRI ,  Akihisa SHIMOMURA ,  Atsushi HIROSE

    IPC: H01L27/108 ,  H01L29/786 ,  H01L23/528

    Abstract: A novel semiconductor device or memory device is provided. Alternatively, a semiconductor device or memory device in which storage capacity per unit area is large is provided. The semiconductor device includes a sense amplifier provided to a semiconductor substrate and a memory cell provided over the sense amplifier. The sense amplifier includes a first transistor. The memory cell includes a capacitor over the semiconductor substrate, a second transistor provided over the capacitor, a conductor, and a groove portion. The capacitor includes a first electrode and a second electrode. The first electrode is formed along the groove portion. The second electrode has a region facing the first electrode in the groove portion. The second transistor includes an oxide semiconductor. One of a source and a drain of the second transistor is electrically connected to the second electrode through the conductor.

    Abstract translation: 提供了一种新颖的半导体器件或存储器件。 或者，提供了其中每单位面积的存储容量大的半导体器件或存储器件。 半导体器件包括提供给半导体衬底的读出放大器和设置在读出放大器上的存储单元。 读出放大器包括第一晶体管。 存储单元包括半导体衬底上的电容器，设置在电容器上的第二晶体管，导体和沟槽部分。 电容器包括第一电极和第二电极。 第一电极沿槽部形成。 第二电极具有在槽部中面向第一电极的区域。 第二晶体管包括氧化物半导体。 第二晶体管的源极和漏极之一通过导体与第二电极电连接。

    SEMICONDUCTOR DEVICE
    26.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20170018560A1

    公开(公告)日：2017-01-19

    申请号：US15278546

    申请日：2016-09-28

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi KATO

    IPC: H01L27/115 ,  H01L29/16 ,  H01L29/24 ,  H01L29/04

    CPC classification number: H01L27/11551 ,  G11C16/0466 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L28/60 ,  H01L29/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/78 ,  H01L29/7869

    Abstract: An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the semiconductor layer having the channel formation region and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction.

    Abstract translation: 目的在于提供具有高集成度的新型结构的半导体装置。 半导体器件包括具有沟道形成区域，与沟道形成区域电连接的源电极和漏电极的半导体层，与沟道形成区域重叠的栅极电极，以及沟道形成区域和沟道形成区域之间的栅极绝缘层 栅电极。 当从平面方向看时，具有沟道形成区域的半导体层的侧表面的一部分和源电极或漏电极的侧表面的一部分基本上对准。

    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
    29.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 有权
    半导体器件和电子器件

    公开(公告)号：US20150294693A1

    公开(公告)日：2015-10-15

    申请号：US14681570

    申请日：2015-04-08

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Takanori MATSUZAKI ,  Hiroki INOUE ,  Shuhei NAGATSUKA ,  Yuto YAKUBO

    IPC: G11C5/02 ,  H01L27/12 ,  G11C5/06 ,  H01L29/24

    CPC classification number: G11C5/025 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/24

    Abstract: Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.

    Abstract translation: 提供一种能够实现面积减小，功耗降低，高速运转的半导体装置。 半导体器件10具有堆叠包括存储电路的电路31和包括放大电路的电路32的结构。 利用这种结构，可以在半导体器件10的面积的增加被抑制的同时将存储电路和放大器电路安装在半导体器件10上。 因此，可以减小半导体器件10的面积。 此外，使用OS晶体管形成电路，从而可以形成具有低截止电流并且可以高速操作的存储电路和放大器电路。 因此，可以实现半导体器件10的功耗的降低和操作速度的提高。

    SEMICONDUCTOR DEVICE
    30.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150279841A1

    公开(公告)日：2015-10-01

    申请号：US14678028

    申请日：2015-04-03

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

    IPC: H01L27/105 ,  H01L29/786 ,  H01L27/12

    CPC classification number: H01L27/1052 ,  G11C5/06 ,  G11C7/12 ,  G11C11/404 ,  G11C11/405 ,  G11C11/565 ,  G11C16/0408 ,  G11C16/10 ,  G11C2211/4016 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/263 ,  H01L29/7869

    Abstract: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

    Abstract translation: 公开了用作多值存储器件的半导体器件，包括：串联连接的存储器单元; 选择存储单元并驱动第二信号线和字线的驱动器电路; 选择写入电位的驱动器电路并将其输出到第一信号线; 读取电路，比较位线的电位和参考电位; 以及产生写入电位和参考电位的电位产生电路。 一个存储单元包括：连接到位线的第一晶体管和源极线; 连接到第一和第二信号线的第二晶体管; 以及连接到字线，位线和源极线的第三晶体管。 第二晶体管包括氧化物半导体层。 第一晶体管的栅电极连接到第二晶体管的源极和漏极之一。

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