Patent search ap:("Siliconware Precision Industries Co. Page Ltd.") AND inv:"Ming-Chen Sun"

21.

发明申请
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME 审中-公开

公开(公告)号：US20170287840A1

公开(公告)日：2017-10-05

申请号：US15621337

申请日：2017-06-13

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai , Wei-Chung Hsiao , Shih-Chao Chiu , Chun-Hsien Lin , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen

IPC: H01L23/538 , H01L23/00

CPC classification number: H01L23/5389 , H01L21/568 , H01L23/3128 , H01L24/19 , H01L24/96 , H01L2224/04105 , H01L2224/16227 , H01L2224/97 , H01L2924/15311 , H01L2224/81

Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.

22.

发明授权
Package structure having a laminated release layer and method for fabricating the same 有权

公开(公告)号：US09673140B2

公开(公告)日：2017-06-06

申请号：US14620328

申请日：2015-02-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Cheng Chen , Ming-Chen Sun , Tzu-Chieh Shen , Shih-Chao Chiu , Wei-Chung Hsiao , Yu-Cheng Pai , Don-Son Jiang

IPC: H01L23/498 , H01L21/48 , H01L23/538 , H01L23/00 , H01L25/10 , H01L25/16

CPC classification number: H01L23/49811 , H01L21/4853 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/92 , H01L25/105 , H01L25/16 , H01L2224/131 , H01L2224/16227 , H01L2224/16235 , H01L2224/16237 , H01L2224/73204 , H01L2224/92125 , H01L2225/1023 , H01L2225/1058 , H01L2225/1076 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1579 , H01L2924/19103 , H01L2924/37001 , H01L2924/014

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.

23.

发明授权
Package substrate, semiconductor package and method of manufacturing the same 有权

公开(公告)号：US09640503B2

公开(公告)日：2017-05-02

申请号：US14837245

申请日：2015-08-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ming-Chen Sun , Chun-Hsien Lin , Tzu-Chieh Shen , Shih-Chao Chiu , Yu-Cheng Pai

IPC: H01L23/00 , H01L21/56 , H01L23/31 , H05K1/11 , H05K3/00 , H05K3/40 , H05K3/20 , H05K3/42

CPC classification number: H01L21/4853 , H01L21/486 , H01L21/563 , H01L23/3114 , H01L23/3121 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/13082 , H01L2224/131 , H01L2224/16238 , H01L2224/81191 , H01L2224/81815 , H01L2224/8182 , H01L2924/15313 , H05K1/111 , H05K3/20 , H05K3/205 , H05K3/428 , H05K2201/0376 , H05K2201/09481 , H05K2201/09563 , H05K2201/10674 , H01L2924/00014 , H01L2924/014

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

24.

发明授权
Coreless packaging substrate and fabrication method thereof 有权
Title translation: 无芯封装基板及其制造方法

公开(公告)号：US09510463B2

公开(公告)日：2016-11-29

申请号：US14583317

申请日：2014-12-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai , Chun-Hsien Lin , Shih-Chao Chiu , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen

IPC: H01L23/498 , H05K3/40 , H05K3/46 , H05K3/20

CPC classification number: H01L21/6835 , H01L21/4857 , H01L21/486 , H01L23/498 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/17 , H01L2221/68345 , H01L2221/68359 , H01L2221/68381 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H05K3/20 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/09563 , H05K2201/10674

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Abstract translation: 提供了一种无芯封装基板，其包括：具有相对的第一和第二表面的电介质层; 所述第一电路层嵌入在所述电介质层中并且从所述电介质层的所述第一表面露出，其中所述第一电路层具有多个第一导电焊盘; 分别形成在第一导电焊盘上的多个突起元件，其中每个突出元件具有被外部导电元件封装的接触表面; 形成在电介质层的第二表面上的第二电路层; 以及形成在电介质层中的多个导电通孔，用于电连接第一电路层和第二电路层。本发明由于突出元件和导电元件之间的大的接触面积而增强了第一导电焊盘和导电元件之间的接合。

25.

发明申请
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开
Title translation: 半导体封装及其制造方法

公开(公告)号：US20160071780A1

公开(公告)日：2016-03-10

申请号：US14603844

申请日：2015-01-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu , Chun-Hsien Lin , Ming-Chen Sun , Yu-Cheng Pai , Tzu-Chieh Shen

IPC: H01L23/31 , H01L23/522

CPC classification number: H01L23/5226 , H01L23/3121 , H01L23/49822 , H01L23/50 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/92 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/32225 , H01L2224/73253 , H01L2224/92242 , H01L2225/06513 , H01L2225/06517 , H01L2924/15153 , H01L2924/15313 , H01L2924/1579 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/014

Abstract: A method of fabricating a semiconductor package is provided, including providing a carrier provided having a circuit layer and a blocking member, forming on the carrier an encapsulating layer having a first surface and a second surface opposing the first surface and encapsulating the circuit layer and the blocking member, with the first surface coupled with the carrier, and removing the carrier and the blocking member to form in the encapsulating layer via the first surface thereof an opening for an electronic component to be received therein. Before the electronic component is disposed in the opening, the circuit layer and the electronic component can be tested in advance, in order to retire the defectives. Therefore, as a defective electronic component is prevented from being disposed in the opening, no defective semiconductor package will be fabricated.

Abstract translation: 提供一种制造半导体封装的方法，包括提供具有电路层和阻挡构件的载体，在载体上形成具有第一表面和与第一表面相对的第二表面的封装层，并封装电路层和阻挡构件，其中第一表面与载体联接，并且移除载体和阻挡构件，以在封装层中经由其第一表面形成用于待接纳在其中的电子部件的开口。在将电子部件设置在开口内之前，可以预先测试电路层和电子部件，以便退出缺陷。因此，由于防止有缺陷的电子元件被布置在开口中，所以不会制造有缺陷的半导体封装。

26.

发明申请
CORELESS PACKAGING SUBSTRATE, POP STRUCTURE, AND METHODS FOR FABRICATING THE SAME 审中-公开
Title translation: 无缝包装基材，POP结构及其制造方法

公开(公告)号：US20150325516A1

公开(公告)日：2015-11-12

申请号：US14464051

申请日：2014-08-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun- Hsien Lin , Shih-Chao Chiu , Yu-cheng Pai , Tzu-Chieh Shen , Ming-Chen Sun

IPC: H01L23/522 , H01L21/56 , H01L23/482 , H01L23/31 , H01L23/498 , H01L21/768

CPC classification number: H01L21/48 , H01L21/56 , H01L21/76897 , H01L23/3128 , H01L23/3157 , H01L23/4824 , H01L23/49811 , H01L23/49822 , H01L23/49833 , H01L23/5226 , H01L23/5389 , H01L25/105 , H01L25/50 , H01L2224/16237 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2224/16225 , H01L2924/00

Abstract: A method for fabricating a coreless packaging substrate is provided, which includes: forming a dielectric layer on a conductive plate having a plurality of conductive pads; forming a circuit layer on the dielectric layer and forming in the dielectric layer a plurality of conductive vias that electrically connect the circuit layer and the conductive pads; and removing a portion of the conductive plate so as to cause the remaining portion of the conductive plate to form a plurality of conductive elements, thereby dispensing with a core layer and reducing the material and fabrication cost.

Abstract translation: 提供了一种无芯封装基板的制造方法，其包括：在具有多个导电焊盘的导电板上形成电介质层; 在电介质层上形成电路层，并在电介质层中形成电连接电路层和导电焊盘的多个导电通孔; 并且去除导电板的一部分以使导电板的剩余部分形成多个导电元件，由此分配芯层并减少材料和制造成本。

27.

发明申请
PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
Title translation: 包装结构及其制造方法

公开(公告)号：US20150287671A1

公开(公告)日：2015-10-08

申请号：US14620328

申请日：2015-02-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Cheng Chen , Ming-Chen Sun , Tzu-Chieh Shen , Shih-Chao Chiu , Wei-Chung Hsiao , Yu-Cheng Pai , Don-Son Jiang

IPC: H01L23/498 , H01L21/48 , H01L23/492

CPC classification number: H01L23/49811 , H01L21/4853 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/92 , H01L25/105 , H01L25/16 , H01L2224/131 , H01L2224/16227 , H01L2224/16235 , H01L2224/16237 , H01L2224/73204 , H01L2224/92125 , H01L2225/1023 , H01L2225/1058 , H01L2225/1076 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1579 , H01L2924/19103 , H01L2924/37001 , H01L2924/014

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.

Abstract translation: 提供了一种制造封装结构的方法，其包括以下步骤：提供具有多个焊盘的载体; 在载体上层叠层压体，其中层压体具有积累部分和尺寸小于组合部分的剥离部分，覆盖接合焊盘的释放部分和积层部分层压在释放部分上，承运人在所述积层部中形成多个导电柱; 以及在所述释放部分上移除所述释放部分和所述积累部分，使得在所述层压体中形成空腔以露出所述接合焊盘，所述导电柱位于所述空腔的周边周围。因此，本发明具有简化的处理。

28.

发明授权
Method of fabricating a packaging substrate including a carrier having two carrying portions 有权

公开(公告)号：US10096491B2

公开(公告)日：2018-10-09

申请号：US14755372

申请日：2015-06-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai , Chun-Hsien Lin , Wei-Chung Hsiao , Ming-Chen Sun , Liang-Yi Hung

IPC: H01L21/48 , H01L21/56 , H01L21/683 , H01L21/78 , H01L23/00 , H01L23/498 , H01L23/31

Abstract: A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement.