Method for cleaning semiconductor structures using hydrocarbon and solvents in a repetitive vapor phase/liquid phase sequence
    24.
    发明授权
    Method for cleaning semiconductor structures using hydrocarbon and solvents in a repetitive vapor phase/liquid phase sequence 失效
    在重复气相/液相序列中使用烃和溶剂清洗半导体结构的方法

    公开(公告)号:US06692579B2

    公开(公告)日:2004-02-17

    申请号:US09764244

    申请日:2001-01-19

    IPC分类号: B08B300

    摘要: A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity. In the pressurized hydrocarbon process, a semiconductor structure is placed into a variable pressure cleaning chamber, having a piston which changes the pressure by reducing or increasing the volume of the chamber. The semiconductor structure first exposed to the hydrocarbon in vapor phase, then the piston is lowered to condense the hydrocarbon. A semiconductor structure can be cleaned by either or both of these processes by repetitive vaporization/condensation cycles.

    摘要翻译: 一种使用与气相清洗剂进行气相冷凝的半导体结构,通过压力变化蒸发的烃或两者的组合来清洗半导体结构的方法。 在热蒸发清洗剂方法中,半导体结构在大气压力的热梯度清洗室内被降低成蒸气层,所述热梯度清洗室通过将蒸气层下方的液体清洗剂加热而形成,并将该液体清洁剂冷却至蒸气层以上 冷凝并返回到热梯度清洗室的底部。 然后将半导体结构升高到蒸气层上方,并且清洁剂在半导体结构的所有表面上冷凝除去杂质,并通过重力返回到室的底部。 在加压烃工艺中,将半导体结构放置在可变压力清洁室中,其具有通过减小或增加室的体积来改变压力的活塞。 半导体结构首先暴露于气相中的烃,然后降低活塞以使烃冷凝。 半导体结构可以通过这些过程中的任一个或两者通过重复的蒸发/冷凝循环进行清洁。

    Method for Making Integrated Circuit Device Using Copper Metallization on 1-3 PZT Composite
    29.
    发明申请
    Method for Making Integrated Circuit Device Using Copper Metallization on 1-3 PZT Composite 审中-公开
    在1-3 PZT复合材料上使用铜金属化的集成电路器件的方法

    公开(公告)号:US20110269307A1

    公开(公告)日:2011-11-03

    申请号:US13098964

    申请日:2011-05-02

    IPC分类号: H01L21/768

    摘要: Provided herein is a method of making an integrated circuit device using copper metallization on 1-3 PZT composite. The method includes providing an overlay of electroplated immersion of gold (Au) to cover copper metal traces, the overlay preventing oxidation on 1:3 PZT composite with material. Also included is the formation of immersion Au nickel electrodes on the 1-3 PZT composite to achieve pad metallization for external connections.

    摘要翻译: 本文提供了在1-3PZT复合材料上制造使用铜金属化的集成电路器件的方法。 该方法包括提供金(Au)的电镀浸渍覆盖铜金属迹线的覆盖层,该覆盖层防止1:3 PZT复合材料与材料的氧化。 还包括在1-3 PZT复合材料上形成浸金Au镍电极,以实现外部连接的焊盘金属化。

    Method for reducing gouging during via formation
    30.
    发明授权
    Method for reducing gouging during via formation 失效
    通孔形成时减少气刨的方法

    公开(公告)号:US06686279B2

    公开(公告)日:2004-02-03

    申请号:US10114680

    申请日:2002-04-01

    IPC分类号: H01L2144

    CPC分类号: H01L21/76831 H01L21/76802

    摘要: A method and apparatus for reducing gouging during via formation. In one embodiment, the present invention is comprised of a method which includes forming an opening into a substrate. The opening is formed extending into the substrate and terminating on at least a portion of a target to which it is desired to form an electrical connection. After the formation of the opening, the present embodiment lines the opening with a liner material. In this embodiment, the liner material is adapted to at least partially fill a portion of the opening which is not landed on the target. The liner material of the present embodiment prevents substantial further etching of the substrate conventionally caused by the opening being at least partially unlanded on the target. Next, the present embodiment subjects the liner material to an etching process such that the liner material is substantially removed from that region of the target where the opening was landed on the target. In this embodiment, liner material residing in the region where the opening is unlanded prevents further gouging of the substrate proximate to the target.

    摘要翻译: 一种用于在通孔形成期间减少气刨的方法和装置。 在一个实施例中,本发明包括一种方法,该方法包括在基底中形成开口。 开口形成为延伸到基板中并终止于期望形成电连接的目标的至少一部分上。 在形成开口之后,本实施例用衬里材料排列开口。 在该实施例中,衬垫材料适于至少部分地填充未着陆在靶上的开口的一部分。 本实施例的衬垫材料防止了通常由开口至少部分地不在目标上引起的基板的进一步蚀刻。 接下来,本实施例使衬里材料进行蚀刻工艺,使得衬里材料基本上从开口落在靶上的靶的区域中去除。 在这个实施例中,位于开口未被覆盖的区域中的衬垫材料防止了靠近靶的衬底进一步的刨削。