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262 条记录 (耗时 0.027 秒)

    Masking process and structures formed thereby
    22.
    发明授权
    Masking process and structures formed thereby 有权
    掩蔽过程和由此形成的结构

    公开(公告)号：US09502249B2

    公开(公告)日：2016-11-22

    申请号：US15047325

    申请日：2016-02-18

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Tsung-Min Huang ,  Chung-Ju Lee

    IPC分类号： H01L21/00 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/768

    CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816

    摘要： A method, e.g., of forming and using a mask, includes forming an inverse mask over a dielectric layer; forming a mask layer conformally over the inverse mask; removing horizontal portions of the mask layer; and after removing the horizontal portions, simultaneously etching the inverse mask and vertical portions of the mask layer. The etching the inverse mask is at a greater rate than the etching the vertical portions of the mask layer. The etching the inverse mask removes the inverse mask, and the etching the vertical portions of the mask layer forms a mask comprising rounded surfaces distal from the dielectric layer. Recesses are formed in the dielectric layer using the mask. Locations of the inverse mask correspond to fewer than all locations of the recesses.

    摘要翻译： 一种例如形成和使用掩模的方法包括在介电层上形成反掩模; 在所述逆掩模上共形成掩模层; 去除所述掩模层的水平部分; 并且在去除水平部分之后，同时蚀刻反掩模和掩模层的垂直部分。 蚀刻反掩模的速度比蚀刻掩模层的垂直部分的速率更大。 蚀刻反掩模去除反掩模，并且蚀刻掩模层的垂直部分形成包括远离电介质层的圆形表面的掩模。 使用掩模在电介质层中形成凹部。 逆掩模的位置对应于凹部的全部位置。

    Method for Integrated Circuit Patterning
    25.
    发明申请
    Method for Integrated Circuit Patterning 有权
    集成电路图案化方法

    公开(公告)号：US20160064240A1

    公开(公告)日：2016-03-03

    申请号：US14934350

    申请日：2015-11-06

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Tsung-Min Huang ,  Chien-Han Wu ,  Chung-Ju Lee ,  Chih-Tsung Shih ,  Jeng-Horng Chen ,  Shinn-Sheng Yu

    IPC分类号： H01L21/308 ,  H01L21/02 ,  H01L21/027

    CPC分类号： H01L21/3086 ,  H01L21/02282 ,  H01L21/0272 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081

    摘要： A method includes forming a resist over a substrate, resulting in a layer of resist scum between the resist and the substrate. The method further includes forming trenches in the resist, wherein at least a portion of the layer of resist scum remains between the trenches and the substrate. The method further includes forming a first material layer in the trenches, wherein the first material layer has a higher etch resistance than the resist in an etching process. The method further includes performing the etching process to the first material layer, the resist, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate.

    摘要翻译： 一种方法包括在衬底上形成抗蚀剂，在抗蚀剂和衬底之间产生抗蚀剂浮渣层。 该方法还包括在抗蚀剂中形成沟槽，其中抗蚀剂浮渣层的至少一部分保留在沟槽和衬底之间。 该方法还包括在沟槽中形成第一材料层，其中第一材料层在蚀刻工艺中具有比抗蚀剂更高的蚀刻电阻。 该方法还包括对第一材料层，抗蚀剂和抗蚀剂浮渣层进行蚀刻处理，由此在衬底上的抗蚀剂浮渣的图案化层上形成图案化的第一材料层。

    Method for integrated circuit patterning
    26.
    发明授权
    Method for integrated circuit patterning 有权
    集成电路图案化方法

    公开(公告)号：US09184054B1

    公开(公告)日：2015-11-10

    申请号：US14262484

    申请日：2014-04-25

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Tsung-Min Huang ,  Chih-Tsung Shih ,  Chung-Ju Lee ,  Chieh-Han Wu ,  Shinn-Sheng Yu ,  Jeng-Horng Chen

    IPC分类号： H01L21/76 ,  H01L21/033

    CPC分类号： H01L21/3086 ,  H01L21/02282 ,  H01L21/0272 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081

    摘要： Provided is a method of patterning a substrate. The method includes forming a resist layer over the substrate, wherein a layer of resist scum forms in between a first portion of the resist layer and the substrate. The method further includes patterning the resist layer to form a plurality of trenches in the first portion, wherein the layer of resist scum provides a floor for the plurality of trenches. The method further includes forming a first material layer in the plurality of trenches, wherein the first material layer has a higher etch resistance than the resist layer and the layer of resist scum. The method further includes etching the first material layer, the resist layer, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate.

    摘要翻译： 提供了图案化基板的方法。 该方法包括在衬底上形成抗蚀剂层，其中在抗蚀剂层的第一部分和衬底之间形成抗蚀剂浮渣层。 该方法还包括图案化抗蚀剂层以在第一部分中形成多个沟槽，其中抗蚀剂浮渣层为多个沟槽提供底板。 该方法还包括在多个沟槽中形成第一材料层，其中第一材料层具有比抗蚀剂层和抗蚀剂浮渣层更高的蚀刻电阻。 该方法还包括蚀刻第一材料层，抗蚀剂层和抗蚀剂浮渣层，从而在衬底上的抗蚀剂浮渣的图案化层上形成图案化的第一材料层。

    Integrated circuit device having a copper interconnect
    28.
    发明授权
    Integrated circuit device having a copper interconnect 有权
    具有铜互连的集成电路器件

    公开(公告)号：US09129967B2

    公开(公告)日：2015-09-08

    申请号：US13668837

    申请日：2012-11-05

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Tsung-Min Huang

    IPC分类号： H01L21/4763 ,  H01L23/532 ,  H01L21/768

    CPC分类号： H01L23/53233 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an interconnect structure of an integrated circuit including providing a first dielectric layer disposed on a semiconductor substrate. A via (or via hole) is etched in the first dielectric layer. A conductive layer including copper is formed that fills the via hole and has a first portion that is disposed on a top surface of the first dielectric layer. A trench is formed in the first portion of the conductive layer to pattern a copper interconnect line disposed on the first dielectric layer. The trench is filled with a second dielectric material. In an embodiment, a barrier layer is self-formed during the removal of a masking element used in the etching of the trench.

    摘要翻译： 一种形成集成电路的互连结构的方法，包括提供设置在半导体衬底上的第一介电层。 在第一电介质层中蚀刻通孔（或通孔）。 形成包括铜的导电层，其填充通孔并且具有设置在第一介电层的顶表面上的第一部分。 在导电层的第一部分中形成沟槽以对布置在第一介电层上的铜互连线进行图案化。 沟槽填充有第二电介质材料。 在一个实施例中，在去除用于蚀刻沟槽的掩模元件期间，阻挡层是自形成的。

    Method For Integrated Circuit Patterning
    30.
    发明申请
    Method For Integrated Circuit Patterning 有权
    集成电路图案化方法

    公开(公告)号：US20150179435A1

    公开(公告)日：2015-06-25

    申请号：US14134027

    申请日：2013-12-19

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chieh-Han Wu ,  Chung-Ju Lee ,  Cheng-Hsiung Tsai ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Tien-I Bao ,  Shau-Lin Shue

    IPC分类号： H01L21/02 ,  H01L21/308 ,  H01L21/027

    CPC分类号： H01L21/76816 ,  H01L21/02104 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802

    摘要： A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.

    摘要翻译： 形成目标图案的方法包括在第一掩模上在衬底上形成多条线，并在该衬底上，多条线上以及多条线的侧壁上形成第一间隔层。 多条线被去除，从而在衬底上提供图案化的第一间隔层。 所述方法还包括在所述图案化的第一间隔层上以及所述图案化的第一间隔层的侧壁上方在所述衬底上形成第二间隔层，以及在所述第二间隔层上形成具有第二掩模的图案化材料层。 由此，图案化材料层和第二间隔层共同限定多个沟槽。