公开(公告)号：US20180350675A1

公开(公告)日：2018-12-06

申请号：US16050168

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76883 ,  H01L21/02074 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/535

Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

公开(公告)号：US09962805B2

公开(公告)日：2018-05-08

申请号：US15136706

申请日：2016-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Kui Chang ,  Fu-Ming Huang ,  Liang-Guang Chen ,  Chun-Chieh Lin

IPC: B24B37/00 ,  B24B37/20 ,  B24B37/005

CPC classification number: B24B37/20 ,  B24B37/005 ,  B24B37/30

Abstract: A polisher head of a polishing apparatus includes a membrane and a first local pressure nodule and a second local pressure nodule physically contacting the membrane. The first local pressure nodule is configured to apply a first local force to the membrane and the second local pressure nodule is configured to apply a second local force to the membrane. The first local pressure nodule and the second local pressure nodule are independently controllable.

公开(公告)号：US09953868B2

公开(公告)日：2018-04-24

申请号：US14988005

申请日：2016-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chien-An Chen ,  Wen-Jiun Liu ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming Hsing Tsai ,  Syun-Ming Jang

IPC: H01L21/321 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76864 ,  H01L21/76882 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a conductive structure includes forming a first opening and a second opening in a dielectric layer on a substrate, wherein the first opening is narrower than the second opening. The method further includes depositing a diffusion barrier layer to line the first opening and the second opening. The method further includes forming a metal layer over the diffusion barrier layer to fill at least portions of the first opening and the second opening, wherein a maximum thickness of the metal layer in the first opening is greater than a maximum thickness of the metal layer in the second opening.

公开(公告)号：US20150187579A1

公开(公告)日：2015-07-02

申请号：US14642968

申请日：2015-03-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rueijer LIN ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

CPC classification number: B81C1/00158 ,  B81B7/008 ,  B81B2207/015 ,  B81B2207/096 ,  B81C1/00246 ,  B81C1/00333 ,  B81C1/00539 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/0127 ,  B81C2203/0742 ,  B81C2203/0778 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02247 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802

Abstract: A method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.

Abstract translation: 在半导体器件制造期间在形成互连的镶嵌工艺中形成氮化钛（TiN）硬掩模的方法，同时控制由TiN硬掩模承载的应力的类型和大小。 TiN硬掩模以多层结构形成，其中通过重复包括TiN和氯PECVD沉积以及N2 / H2等离子体气体处理的工艺循环来连续形成每个子层。 在其形成期间，通过控制TiN子层的数量和等离子体气体处理持续时间来控制由TiN硬掩模承载的应力，使得应力可以平衡在常规制备的TiN硬掩模上预期的预定外部应力 ，这导致沟槽侧壁变形，沟槽开口收缩和间隙填充问题。

公开(公告)号：US12002684B2

公开(公告)日：2024-06-04

申请号：US18057728

申请日：2022-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Liang-Guang Chen ,  Kei-Wei Chen ,  Hung Yen ,  Ting-Hsun Chang ,  Chi-Hsiang Shen ,  Li-Chieh Wu ,  Chi-Jen Liu

IPC: H01L21/321 ,  B24B37/04 ,  B24B37/10 ,  C09G1/02

CPC classification number: H01L21/3212 ,  B24B37/044 ,  B24B37/107 ,  C09G1/02

Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.

公开(公告)号：US11772228B2

公开(公告)日：2023-10-03

申请号：US16746292

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Hsun Chang ,  Hung Yen ,  Chi-Hsiang Shen ,  Fu-Ming Huang ,  Chun-Chieh Lin ,  Tsung Hsien Chang ,  Ji Cui ,  Liang-Guang Chen ,  Chih Hung Chen ,  Kei-Wei Chen

IPC: B24B37/16 ,  B24B57/02 ,  B24B37/015 ,  H01L21/306

CPC classification number: B24B37/16 ,  B24B37/015 ,  B24B57/02 ,  H01L21/30625

Abstract: A chemical mechanical planarization apparatus includes a multi-zone platen comprising a plurality of individually controlled concentric toroids. The rotation direction, rotation speed, applied force, relative height, and temperature of each concentric toroid is individually controlled. Concentric polishing pads are affixed to an upper surface of each of the individually controlled concentric toroids. The chemical mechanical planarization apparatus includes a single central slurry source or includes individual slurry sources for each individually controlled concentric toroid.

公开(公告)号：US20210220964A1

公开(公告)日：2021-07-22

申请号：US16746292

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Hsun Chang ,  Hung Yen ,  Chi-Hsiang Shen ,  Fu-Ming Huang ,  Chun-Chieh Lin ,  Tsung Hsien Chang ,  Ji Cui ,  Liang-Guang Chen ,  Chih Hung Chen ,  Kei-Wei Chen

IPC: B24B37/16 ,  H01L21/306 ,  B24B37/015 ,  B24B57/02

Abstract: A chemical mechanical planarization apparatus includes a multi-zone platen comprising a plurality of individually controlled concentric toroids. The rotation direction, rotation speed, applied force, relative height, and temperature of each concentric toroid is individually controlled. Concentric polishing pads are affixed to an upper surface of each of the individually controlled concentric toroids. The chemical mechanical planarization apparatus includes a single central slurry source or includes individual slurry sources for each individually controlled concentric toroid.

公开(公告)号：US20190244804A1

公开(公告)日：2019-08-08

申请号：US16390691

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Ming Huang ,  Liang-Guang Chen ,  Ting-Kui Chang ,  Chun-Chieh Lin

IPC: H01L21/02 ,  H01L21/67 ,  B08B1/00 ,  B08B1/04 ,  H01L21/687 ,  B08B3/04 ,  H01L21/306

CPC classification number: H01L21/02043 ,  B08B1/002 ,  B08B1/04 ,  B08B3/04 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/30625 ,  H01L21/67028 ,  H01L21/67046 ,  H01L21/67092 ,  H01L21/687

Abstract: A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.

公开(公告)号：US20180151427A1

公开(公告)日：2018-05-31

申请号：US15395057

申请日：2016-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76883 ,  H01L21/76802 ,  H01L21/76895 ,  H01L23/535

Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

公开(公告)号：US09941199B2

公开(公告)日：2018-04-10

申请号：US15600941

申请日：2017-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ya-Lien Lee ,  Chun-Chieh Lin

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L29/40 ,  H01L23/532

CPC classification number: H01L23/5222 ,  H01L21/76813 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76879 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a first conductive line, a dielectric layer over the first conductive line, a diffusion barrier layer in the dielectric layer, and a second conductive line in the dielectric layer. The second conductive line includes a first portion of the diffusion barrier layer. A via is underlying the second conductive line and electrically couples the second conductive line to the first conductive line. The via includes a second portion of the diffusion barrier layer, with the second portion of the diffusion barrier layer having a bottom end higher than a bottom surface of the via.