公开(公告)号：US20170287917A1

公开(公告)日：2017-10-05

申请号：US15091546

申请日：2016-04-05

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/265 ,  H01L29/06 ,  H01L21/8249 ,  H01L21/266 ,  H01L27/082 ,  H01L27/06

CPC classification number: H01L27/1104 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/092 ,  H01L27/1116 ,  H01L29/0638 ,  H01L29/66068 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7802

Abstract: An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants are blocked from the logic MOS transistors.

公开(公告)号：US09761581B1

公开(公告)日：2017-09-12

申请号：US15060261

申请日：2016-03-03

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Douglas Tad Grider, III

IPC: H01L21/8238 ,  H01L27/06 ,  H01L21/8249 ,  H01L21/28 ,  H01L49/02 ,  H01L21/3215 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/167 ,  H01L29/06 ,  H01L27/092 ,  H01L29/732

CPC classification number: H01L27/0635 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/8249 ,  H01L27/0629 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0847 ,  H01L29/1004 ,  H01L29/167 ,  H01L29/66143 ,  H01L29/66272 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/732

Abstract: A method of forming an IC includes providing a field dielectric in a portion of a semiconductor surface, a bipolar or Schottky diode (BSD) class device area, a CMOS transistor area, and a resistor area. A polysilicon layer is deposited to provide a polysilicon gate area for MOS transistors in the CMOS transistor area, over the BSD class device area, and over the field dielectric for providing a polysilicon resistor in the resistor area. A first mask pattern is formed on the polysilicon layer. Using the first mask pattern, first implanting (I1) of the polysilicon resistor providing a first projected range (RP1) RP1. I2 provides a CMOS implant into the semiconductor surface layer in the CMOS transistor area and/or a BSD implant into the semiconductor surface layer in the BSD area.

公开(公告)号：US09589959B2

公开(公告)日：2017-03-07

申请号：US14497601

申请日：2014-09-26

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Sunitha Venkataraman ,  David L. Catlett, Jr.

IPC: H01L23/62 ,  H01L27/092 ,  H01L27/06 ,  H01L27/08 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0629 ,  H01L27/0811 ,  H01L27/0814 ,  H01L27/0928 ,  H01L29/0649

Abstract: An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.

Abstract translation: 具有浅沟槽隔离，低电容，ESD保护二极管的集成电路。 集成电路具有隔离栅极空间，低电容，ESD保护二极管。 集成电路具有隔离的栅极空间，低电容，ESD保护二极管与浅沟槽隔离，低电容，ESD保护二极管。

公开(公告)号：US20160133622A1

公开(公告)日：2016-05-12

申请号：US14996360

申请日：2016-01-15

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L27/06 ,  H01L29/49 ,  H01L29/47 ,  H01L29/872 ,  H01L29/36

CPC classification number: H01L27/0629 ,  H01L29/36 ,  H01L29/47 ,  H01L29/4966 ,  H01L29/66143 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/872

Abstract: An integrated circuit and method with a metal gate transistor and with a Schottky diode where the metal used to form the Schottky diode is the metal used to form the metal gate.

公开(公告)号：US09147764B2

公开(公告)日：2015-09-29

申请号：US14497498

申请日：2014-09-26

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L27/088 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7836 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7833 ,  H01L29/7835

Abstract: An integrated circuit includes MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit includes MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel.

Abstract translation: 集成电路包括具有铟，碳，氮和卤素掺杂物中的至少一种的MOS和DEMOS晶体管，其提高覆盖在DEMOS晶体管沟道上的DEMOS晶体管栅极的一部分的阈值电压。 集成电路包括具有铟，碳，氮和卤素掺杂物中的至少一种的MOS和LDMOS晶体管，其提高覆盖在DEMOS晶体管沟道上的LDMOS晶体管栅极的一部分的阈值电压。 用具有铟，碳，氮和卤素掺杂物中的至少一种的MOS和DEMOS晶体管形成集成电路的方法提高了覆盖在DEMOS晶体管沟道上的DEMOS晶体管栅极的一部分的阈值电压。 用具有铟，碳，氮和卤素掺杂物中的至少一种的MOS和LDMOS晶体管形成集成电路的方法提高了覆盖在DEMOS晶体管沟道上的LDMOS晶体管栅极的一部分的阈值电压。

公开(公告)号：US20150187903A1

公开(公告)日：2015-07-02

申请号：US14578722

申请日：2014-12-22

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Mahalingam Nandakumar

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L21/02 ,  H01L29/49 ,  H01L21/3105

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/7833

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench

Abstract translation: 替代金属栅极晶体管结构和方法，其具有薄的氮化硅侧壁并且在替换栅极晶体管沟槽的垂直侧壁上具有很少或不具有高k电介质

公开(公告)号：US12154987B2

公开(公告)日：2024-11-26

申请号：US17548827

申请日：2021-12-13

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/3115

Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.

公开(公告)号：US20240290844A1

公开(公告)日：2024-08-29

申请号：US18652020

申请日：2024-05-01

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Alexei Sadovnikov ,  Henry Litzmann Edwards ,  Jarvis Benjamin Jacobs

IPC: H01L29/26 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/26 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device including drain extended metal oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region each having a first dopant type spaced apart along a surface of a semiconductor material having a second opposite conductivity type. A gate electrode over the semiconductor material surface between the source region and the drain region. A diffusion suppression implant region in the semiconductor material extends from the source region under the gate electrode. The diffusion suppression implant region includes a body region having the second opposite conductivity type and comprises at least one of carbon, nitrogen, and fluorine.

公开(公告)号：US12009423B2

公开(公告)日：2024-06-11

申请号：US17135541

申请日：2020-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Edward Hornung ,  Mahalingam Nandakumar

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/167 ,  H01L29/66492

Abstract: An integrated circuit is fabricated by forming transistors having gates of orthogonal orientations and implanting, at two first rotations, a first pocket implant using a first dopant type with a masking pattern on a substrate surface layer, the two first rotations respectively forming two first pocket implantation angles and two first pocket implantation beam orientations, and implanting, at two second rotations, a retrograde gate-edge diode leakage (GDL) reduction pocket implant using a second dopant type with the masking pattern on the substrate surface layer, the two second rotations respectively forming two GDL-reduction implantation angles and two GDL-reduction implantation beam orientations. Owing to the different symmetries in implantation angles seen by the two orientations of transistors, leakage is reduced for transistors of both orientations and mismatch is maintained for transistors of one of the orientations, making these transistors suitable for use in analog circuits requiring matched pairs of transistors.

公开(公告)号：US20230386923A1

公开(公告)日：2023-11-30

申请号：US18446176

申请日：2023-08-08

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L21/822 ,  H01L21/266 ,  H01L21/265 ,  H01L27/01

CPC classification number: H01L21/822 ,  H01L21/266 ,  H01L21/26513 ,  H01L27/013

Abstract: Fabrication of an integrated circuit includes forming a photoresist layer over a substrate. Target regions defined on the substrate are exposed using a reticle that defines a first exposure window for a first doped structure of a first type; the first exposure window has a first plurality of openings and a first plurality of dopant blocking regions. A respective exposure dose for each of the target regions is determined by an exposure map and provides controlled variations in the size of the first plurality of openings across the plurality of target regions. Subsequent to the exposure and to developing the photoresist, a dopant is implanted into the substrate through the first plurality of openings.