公开(公告)号：US20160179699A1

公开(公告)日：2016-06-23

申请号：US14581487

申请日：2014-12-23

Applicant: Texas Instruments Incorporated

Inventor： Ramakrishnan Venkatasubramanian ,  Oluleye Olorode

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/681 ,  G06F2212/684

Abstract: This invention hides the page miss translation latency for program fetches. In this invention whenever an access is requested by CPU that crosses a memory page boundary, the L1I cache controller request a next page translation along with the current page. This pipelines requests to the μTLB without waiting for L1I cache controller to begin processing the next page requests. This becomes a deterministic prefetch of the second page translation request. The translation information for the second page is stored locally in L1I cache controller and used when the access crosses the next page boundary.

Abstract translation: 本发明隐藏程序提取的页面未命中转换延迟。 在本发明中，只要CPU通过存取页面边界的请求，L1I高速缓存控制器与当前页一起请求下一页翻译。 该管道请求到μTLB，而不等待L1I缓存控制器开始处理下一页请求。 这成为第二页翻译请求的确定性预取。 第二页的翻译信息本地存储在L1I高速缓存控制器中，当访问跨越下一页边界时使用。

公开(公告)号：US12072812B2

公开(公告)日：2024-08-27

申请号：US17237391

申请日：2021-04-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/30 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1045 ,  G06F17/16 ,  H03H17/06 ,  G06F15/78

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.

公开(公告)号：US20230409435A1

公开(公告)日：2023-12-21

申请号：US18239880

申请日：2023-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan Varadarajan ,  Ramakrishnan Venkatasubramanian ,  Varun Singh

IPC: G06F11/14 ,  H03M7/30

CPC classification number: G06F11/1448 ,  H03M7/30 ,  G06F2201/82

Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.

公开(公告)号：US11748202B2

公开(公告)日：2023-09-05

申请号：US17901337

申请日：2022-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan Varadarajan ,  Ramakrishnan Venkatasubramanian ,  Varun Singh

IPC: G06F11/14 ,  H03M7/30

CPC classification number: G06F11/1448 ,  H03M7/30 ,  G06F2201/82

Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.

公开(公告)号：US20230244611A1

公开(公告)日：2023-08-03

申请号：US18083703

申请日：2022-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Joseph Raymond Michael Zbiciak

IPC: G06F12/1081 ,  G06F7/483 ,  G06F9/30 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/3296 ,  H03K21/00 ,  G06F12/02 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0815

CPC classification number: G06F12/1081 ,  G06F7/483 ,  G06F9/3012 ,  H03M13/353 ,  H03M13/2903 ,  G06F11/1064 ,  G06F13/1605 ,  G06F13/18 ,  H03K19/0016 ,  G06F1/3296 ,  H03K21/00 ,  G06F12/0246 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0815 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/364

Abstract: A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

公开(公告)号：US11474944B2

公开(公告)日：2022-10-18

申请号：US17151857

申请日：2021-01-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian ,  Hung Ong

IPC: G06F12/0862 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0888 ,  G06F12/1027

Abstract: This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.

公开(公告)号：US11436090B2

公开(公告)日：2022-09-06

申请号：US17125244

申请日：2020-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan Varadarajan ,  Ramakrishnan Venkatasubramanian ,  Varun Singh

IPC: G06F11/14 ,  H03M7/30

Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.

公开(公告)号：US20210141732A1

公开(公告)日：2021-05-13

申请号：US17151857

申请日：2021-01-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian ,  Hung Ong

IPC: G06F12/0862 ,  G06F12/0875 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0815

Abstract: This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.

公开(公告)号：US10713180B2

公开(公告)日：2020-07-14

申请号：US15991241

申请日：2018-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Raguram Damodaran ,  Ramakrishnan Venkatasubramanian ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F12/1081 ,  G06F7/483 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/3296 ,  H03K21/00 ,  G06F12/02 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0815 ,  G06F13/364

Abstract: A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

公开(公告)号：US20200167288A1

公开(公告)日：2020-05-28

申请号：US16775479

申请日：2020-01-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian

IPC: G06F12/0862 ,  G06F12/1027 ,  G06F9/38 ,  G06F12/02 ,  G06F12/0871

Abstract: Disclosed embodiments provide a technique in which a memory controller determines whether a fetch address is a miss in an L1 cache and, when a miss occurs, allocates a way of the L1 cache, determines whether the allocated way matches a scoreboard entry of pending service requests, and, when such a match is found, determine whether a request address of the matching scoreboard entry matches the fetch address. When the matching scoreboard entry also has a request address matching the fetch address, the scoreboard entry is modified to a demand request.