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    INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES
    21.
    发明申请
    INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES 有权
    具有由两个光刻过程产生的三维特征的互连结构

    公开(公告)号：US20090294982A1

    公开(公告)日：2009-12-03

    申请号：US12538114

    申请日：2009-08-08

    申请人： Matthew E. Colburn ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

    发明人： Matthew E. Colburn ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

    IPC分类号： H01L23/522

    CPC分类号： H01L23/53238 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an interlayer dielectric onto the semiconductor substrate, forming a first pattern within the interlayer dielectric material by a first lithographic process that results in both via features and ternary features being formed in the interconnect structure. The method further includes forming a second pattern within the interlayer dielectric material by a second lithographic process to form line features within the interconnect structure. Hence the method forms the three separate distinct patterned structures using only two lithographic processes for each interconnect level.

    摘要翻译： 一种制造互连结构的方法，用于将半导体衬底互连以具有三个不同的图案化结构，使得互连结构既提供低k和高结构完整性。 该方法包括在半导体衬底上沉积层间电介质，通过第一光刻工艺在层间电介质材料内形成第一图案，该第一光刻工艺导致在互连结构中形成通孔特征和三元特征。 该方法还包括通过第二光刻工艺在层间电介质材料内形成第二图案以在互连结构内形成线特征。 因此，该方法仅对每个互连级别仅使用两个光刻工艺形成三个独立的不同图案结构。

    METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY
    22.
    发明申请
    METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY 审中-公开
    用于实现超低K材料和生产的结构的硬掩模自由集成的方法

    公开(公告)号：US20070249156A1

    公开(公告)日：2007-10-25

    申请号：US11672608

    申请日：2007-02-08

    申请人： Griselda Bonilla ,  Stephen M. Gates ,  Shom Ponoth ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

    发明人： Griselda Bonilla ,  Stephen M. Gates ,  Shom Ponoth ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76826 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76883

    摘要： A method is described for the repair of process induced damage sustained by low-k organosilicate dielectrics as a result of reactive ion etch, resist strip, wet clean and CMP operations in a hard mask free integration of these dielectrics into microelectronic interconnect structures incorporating a dielectric cap which is an etch stop and barrier layer. In situ reaction of the damaged regions with a suitable silylation agent just prior to a passivation barrier cap deposition is proposed as the most efficacious means to repair all the damage sustained by the dielectric. Variations of this method which include ex situ rather than in situ silylation are also described for use with hard mask free integration with selective barrier caps.

    摘要翻译： 描述了一种用于修复由低k有机硅酸盐电介质持续的过程诱导的损伤作为反应离子蚀刻，抗蚀剂条，湿清洁和CMP操作在将这些电介质纳入包含电介质的微电子互连结构的硬掩模中的CMP操作的方法 盖是蚀刻停止层和阻挡层。 在钝化阻挡层沉积之前，损伤区域与合适的甲硅烷基化剂的原位反应被提出作为修复由电介质所承受的所有损伤的最有效手段。 还描述了包括异位原位甲硅烷基化的这种方法的变化，用于与选择性屏障帽的硬掩模自由积分。

    Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics
    25.
    发明授权
    Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics 有权
    低k互连结构由多层旋涂多孔电介质组成

    公开(公告)号：US06716742B2

    公开(公告)日：2004-04-06

    申请号：US10292205

    申请日：2002-11-12

    申请人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    发明人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    IPC分类号： H01L214763

    CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

    摘要翻译： 提供了其中不存在微沟槽的低k电介质金属导体互连结构以及形成这种结构的方法。 具体地说，上述结构是通过提供一种互连结构来实现的，所述互连结构至少包括多层电介质材料，所述多层电介质材料依次应用于单个旋涂工具中，然后在单个步骤中固化，并且多个图案化的金属导体在多层纺丝 - 电介质。 使用具有位于具有第一原子组成的多孔低k电介质的线路和通孔电介质层之间的第二原子组成的掩埋蚀刻停止层来获得对导体电阻的控制。 本发明的互连结构还包括有助于形成双镶嵌型互连结构的硬掩模。 选择第一和第二组合物以获得至少10至1或更高的蚀刻选择性，并且选自具有特定原子组成和其它可发现量的多孔低k有机或无机材料的特定组。