公开(公告)号：US07748110B2

公开(公告)日：2010-07-06

申请号：US11826758

申请日：2007-07-18

申请人： Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama ,  Koichi Hirano ,  Osamu Shibata ,  Takeshi Nakayama ,  Yoshiyuki Saito

发明人： Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama ,  Koichi Hirano ,  Osamu Shibata ,  Takeshi Nakayama ,  Yoshiyuki Saito

IPC分类号： H05K3/36

CPC分类号： H05K3/403 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H01R13/2414 ,  H05K1/0218 ,  H05K1/0284 ,  H05K1/141 ,  H05K1/145 ,  H05K1/182 ,  H05K3/20 ,  H05K3/3442 ,  H05K3/361 ,  H05K3/366 ,  H05K3/368 ,  H05K2201/043 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/055 ,  H05K2201/056 ,  H05K2201/09036 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2203/302 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49208 ,  H01L2924/00

摘要： A connection member can be produced without a via-forming step. The connection member includes an insulating substrate which has an upper surface, a lower surface opposed to the upper surface, and a side surface which connects these surfaces; and at least one wiring which extends from the upper surface to the lower surface through the side surface.

摘要翻译： 可以在没有通孔形成步骤的情况下制造连接构件。 连接构件包括绝缘基板，其具有上表面，与上表面相对的下表面和连接这些表面的侧表面; 以及至少一个通过侧面从上表面延伸到下表面的布线。

公开(公告)号：US20070243664A1

公开(公告)日：2007-10-18

申请号：US11579299

申请日：2006-03-07

申请人： Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita ,  Seiichi Nakatani

发明人： Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita ,  Seiichi Nakatani

IPC分类号： H05K3/34 ,  H01L21/00 ,  H01L21/44 ,  H05K3/00

CPC分类号： H01L21/563 ,  B23K35/0244 ,  H01L21/67144 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/133 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2224/83886 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/30105 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/1361 ,  Y02P70/613 ,  Y10T29/53178 ,  H01L2224/05599

摘要： [Problem] To provide a flip-chip mounting method and a bump formation method applicable to flip-chip mounting of a next generation LSI and having high productivity and high reliability. [Means for Solving Problem] A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals. Thereafter, the semiconductor chip 20 and the circuit board 21 are taken out of the dipping bath 40, and the melted resin 14 having permeated into the gap between the semiconductor chip 20 and the circuit board 21 is cured, so as to complete a flip-chip mounting body.

摘要翻译： [问题]提供一种适用于下一代LSI的倒装安装并具有高生产率和高可靠性的倒装芯片安装方法和凸块形成方法。 解决问题的手段具有多个电极端子12的半导体芯片20被保持为具有多个连接端子11的电路板21，其间设置有给定的间隙，并且半导体芯片20和电路板21 将该状态浸渍在包含熔融的焊料颗粒的熔融树脂14的浸渍浴40中一段给定的时间。 在该浸渍过程中，熔融的焊料颗粒自组装在电路板21的连接端子11和半导体芯片20的电极端子12之间，从而在这些端子之间形成连接器22。 此后，半导体芯片20和电路板21从浸渍浴40中取出，并且已经渗透到半导体芯片20和电路板21之间的间隙中的熔融树脂14固化， 芯片安装体。

公开(公告)号：US08691683B2

公开(公告)日：2014-04-08

申请号：US13046151

申请日：2011-03-11

申请人： Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita ,  Seiichi Nakatani

发明人： Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita ,  Seiichi Nakatani

IPC分类号： H01L21/56

CPC分类号： H01L21/563 ,  B23K35/0244 ,  H01L21/67144 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/133 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2224/83886 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/30105 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/1361 ,  Y02P70/613 ,  Y10T29/53178 ,  H01L2224/05599

摘要： [Means for Solving Problem] A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals. Thereafter, the semiconductor chip 20 and the circuit board 21 are taken out of the dipping bath 40, and the melted resin 14 having permeated into the gap between the semiconductor chip 20 and the circuit board 21 is cured, so as to complete a flip-chip mounting body.

摘要翻译： 解决问题的手段具有多个电极端子12的半导体芯片20被保持为具有多个连接端子11的电路板21，其间设置有给定的间隙，半导体芯片20和电路板21 将该状态浸渍在包含熔融的焊料颗粒的熔融树脂14的浸渍浴40中一段给定的时间。 在该浸渍过程中，熔融的焊料颗粒自组装在电路板21的连接端子11和半导体芯片20的电极端子12之间，从而在这些端子之间形成连接器22。 此后，半导体芯片20和电路板21从浸渍浴40中取出，并且已经渗透到半导体芯片20和电路板21之间的间隙中的熔融树脂14固化， 芯片安装体。

公开(公告)号：US20110049598A1

公开(公告)日：2011-03-03

申请号：US12939729

申请日：2010-11-04

申请人： Koichi HIRANO ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi HIRANO ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L29/786

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US20100276691A1

公开(公告)日：2010-11-04

申请号：US12746440

申请日：2009-07-22

申请人： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano ,  Yoshihisa Yamashita ,  Shingo Komatsu

发明人： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano ,  Yoshihisa Yamashita ,  Shingo Komatsu

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/77

CPC分类号： H01L29/78603 ,  H01L24/19 ,  H01L24/82 ,  H01L27/1218 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78681 ,  H01L29/7869 ,  H01L51/0024 ,  H01L51/003 ,  H01L51/0097 ,  H01L51/0541 ,  H01L51/0545 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： A method for fabricating a flexible semiconductor device includes: preparing a layered film 80 including a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40 which are sequentially formed; etching the first metal layer 10 to form a gate electrode 12g; compression bonding a resin layer 50 to a surface of the layered film 80 provided with the gate electrode 12g to allow the gate electrode 12g to be embedded in the resin layer 50; and etching the second metal layer 40 to form a source electrode 42s and a drain electrode 42d, wherein the inorganic insulating layer 20 on the gate electrode 12g functions as a gate insulating film 22, and the semiconductor layer 30 between the source electrode 42s and drain electrode 42d on the inorganic insulating layer 20 functions as a channel 32.

摘要翻译： 一种制造柔性半导体器件的方法包括：制备包括依次形成的第一金属层10，无机绝缘层20，半导体层30和第二金属层40的层状膜80; 蚀刻第一金属层10以形成栅电极12g; 将树脂层50压接到设置有栅电极12g的层叠膜80的表面，以使栅电极12g嵌入树脂层50中; 并且蚀刻第二金属层40以形成源电极42s和漏电极42d，其中栅电极12g上的无机绝缘层20用作栅极绝缘膜22，并且源电极42s和漏极之间的半导体层30 无机绝缘层20上的电极42d用作通道32。

公开(公告)号：US07981528B2

公开(公告)日：2011-07-19

申请号：US11848407

申请日：2007-08-31

申请人： Seiichi Nakatani ,  Yoshihisa Yamashita ,  Takashi Ichiryu ,  Koichi Hirano

发明人： Seiichi Nakatani ,  Yoshihisa Yamashita ,  Takashi Ichiryu ,  Koichi Hirano

IPC分类号： B32B15/00

CPC分类号： G06K19/07749 ,  G06K19/07771 ,  Y10T428/24355 ,  Y10T428/32

摘要： A water-repelling layer is formed on a resin film, and a stripe pattern region is formed so as to be positioned within a surface region of the water-repelling layer and so as to be relatively hydrophilic with respect to water repellency of the water-repelling layer. A magnetic stripe pattern is formed of needle-shaped magnetic grains oriented and aggregated in the stripe pattern region. The needle-shaped magnetic grains are arranged in a desirable state in a predetermined stripe pattern, with a high magnetic permeability and a magnetic sheet with stripe-arranged magnetic grains that is thin and flexible is obtained.

摘要翻译： 在树脂膜上形成防水层，并且形成条纹图案区域，以便位于防水层的表面区域内，并且相对于水溶性防水层的防水性而相对亲水， 排斥层。 磁条图案由在条纹图案区域中定向和聚集的针状磁性颗粒形成。 针状磁性颗粒以预定的条纹图案被布置成期望的状态，具有高磁导率，并且获得薄且柔性的带状排列的磁性颗粒的磁性片。

公开(公告)号：US08617943B2

公开(公告)日：2013-12-31

申请号：US12746440

申请日：2009-07-22

申请人： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano ,  Yoshihisa Yamashita ,  Shingo Komatsu

发明人： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano ,  Yoshihisa Yamashita ,  Shingo Komatsu

IPC分类号： H01L21/00

CPC分类号： H01L29/78603 ,  H01L24/19 ,  H01L24/82 ,  H01L27/1218 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78681 ,  H01L29/7869 ,  H01L51/0024 ,  H01L51/003 ,  H01L51/0097 ,  H01L51/0541 ,  H01L51/0545 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： A method for fabricating a flexible semiconductor device includes: preparing a layered film 80 including a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40 which are sequentially formed; etching the first metal layer 10 to form a gate electrode 12g; compression bonding a resin layer 50 to a surface of the layered film 80 provided with the gate electrode 12g to allow the gate electrode 12g to be embedded in the resin layer 50; and etching the second metal layer 40 to form a source electrode 42s and a drain electrode 42d, wherein the inorganic insulating layer 20 on the gate electrode 12g functions as a gate insulating film 22, and the semiconductor layer 30 between the source electrode 42s and drain electrode 42d on the inorganic insulating layer 20 functions as a channel 32.

摘要翻译： 一种制造柔性半导体器件的方法包括：制备包括依次形成的第一金属层10，无机绝缘层20，半导体层30和第二金属层40的层状膜80; 蚀刻第一金属层10以形成栅电极12g; 将树脂层50压接到设置有栅电极12g的层叠膜80的表面，以使栅电极12g嵌入树脂层50中; 并且蚀刻第二金属层40以形成源电极42s和漏电极42d，其中栅电极12g上的无机绝缘层20用作栅极绝缘膜22，并且源电极42s和漏极之间的半导体层30 无机绝缘层20上的电极42d用作通道32。

公开(公告)号：US07977741B2

公开(公告)日：2011-07-12

申请号：US12939729

申请日：2010-11-04

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L29/786

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US07851281B2

公开(公告)日：2010-12-14

申请号：US12518602

申请日：2008-10-01

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L21/336

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US20100012936A1

公开(公告)日：2010-01-21

申请号：US12518602

申请日：2008-10-01

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/8234 ,  B32B3/02

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。