公开(公告)号：US20110049598A1

公开(公告)日：2011-03-03

申请号：US12939729

申请日：2010-11-04

申请人： Koichi HIRANO ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi HIRANO ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L29/786

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US08617943B2

公开(公告)日：2013-12-31

申请号：US12746440

申请日：2009-07-22

申请人： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano ,  Yoshihisa Yamashita ,  Shingo Komatsu

发明人： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano ,  Yoshihisa Yamashita ,  Shingo Komatsu

IPC分类号： H01L21/00

CPC分类号： H01L29/78603 ,  H01L24/19 ,  H01L24/82 ,  H01L27/1218 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78681 ,  H01L29/7869 ,  H01L51/0024 ,  H01L51/003 ,  H01L51/0097 ,  H01L51/0541 ,  H01L51/0545 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： A method for fabricating a flexible semiconductor device includes: preparing a layered film 80 including a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40 which are sequentially formed; etching the first metal layer 10 to form a gate electrode 12g; compression bonding a resin layer 50 to a surface of the layered film 80 provided with the gate electrode 12g to allow the gate electrode 12g to be embedded in the resin layer 50; and etching the second metal layer 40 to form a source electrode 42s and a drain electrode 42d, wherein the inorganic insulating layer 20 on the gate electrode 12g functions as a gate insulating film 22, and the semiconductor layer 30 between the source electrode 42s and drain electrode 42d on the inorganic insulating layer 20 functions as a channel 32.

摘要翻译： 一种制造柔性半导体器件的方法包括：制备包括依次形成的第一金属层10，无机绝缘层20，半导体层30和第二金属层40的层状膜80; 蚀刻第一金属层10以形成栅电极12g; 将树脂层50压接到设置有栅电极12g的层叠膜80的表面，以使栅电极12g嵌入树脂层50中; 并且蚀刻第二金属层40以形成源电极42s和漏电极42d，其中栅电极12g上的无机绝缘层20用作栅极绝缘膜22，并且源电极42s和漏极之间的半导体层30 无机绝缘层20上的电极42d用作通道32。

公开(公告)号：US20100276691A1

公开(公告)日：2010-11-04

申请号：US12746440

申请日：2009-07-22

申请人： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano ,  Yoshihisa Yamashita ,  Shingo Komatsu

发明人： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano ,  Yoshihisa Yamashita ,  Shingo Komatsu

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/77

CPC分类号： H01L29/78603 ,  H01L24/19 ,  H01L24/82 ,  H01L27/1218 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78681 ,  H01L29/7869 ,  H01L51/0024 ,  H01L51/003 ,  H01L51/0097 ,  H01L51/0541 ,  H01L51/0545 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： A method for fabricating a flexible semiconductor device includes: preparing a layered film 80 including a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40 which are sequentially formed; etching the first metal layer 10 to form a gate electrode 12g; compression bonding a resin layer 50 to a surface of the layered film 80 provided with the gate electrode 12g to allow the gate electrode 12g to be embedded in the resin layer 50; and etching the second metal layer 40 to form a source electrode 42s and a drain electrode 42d, wherein the inorganic insulating layer 20 on the gate electrode 12g functions as a gate insulating film 22, and the semiconductor layer 30 between the source electrode 42s and drain electrode 42d on the inorganic insulating layer 20 functions as a channel 32.

摘要翻译： 一种制造柔性半导体器件的方法包括：制备包括依次形成的第一金属层10，无机绝缘层20，半导体层30和第二金属层40的层状膜80; 蚀刻第一金属层10以形成栅电极12g; 将树脂层50压接到设置有栅电极12g的层叠膜80的表面，以使栅电极12g嵌入树脂层50中; 并且蚀刻第二金属层40以形成源电极42s和漏电极42d，其中栅电极12g上的无机绝缘层20用作栅极绝缘膜22，并且源电极42s和漏极之间的半导体层30 无机绝缘层20上的电极42d用作通道32。

公开(公告)号：US07977741B2

公开(公告)日：2011-07-12

申请号：US12939729

申请日：2010-11-04

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L29/786

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US07851281B2

公开(公告)日：2010-12-14

申请号：US12518602

申请日：2008-10-01

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L21/336

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US20100012936A1

公开(公告)日：2010-01-21

申请号：US12518602

申请日：2008-10-01

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/8234 ,  B32B3/02

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US07981528B2

公开(公告)日：2011-07-19

申请号：US11848407

申请日：2007-08-31

申请人： Seiichi Nakatani ,  Yoshihisa Yamashita ,  Takashi Ichiryu ,  Koichi Hirano

发明人： Seiichi Nakatani ,  Yoshihisa Yamashita ,  Takashi Ichiryu ,  Koichi Hirano

IPC分类号： B32B15/00

CPC分类号： G06K19/07749 ,  G06K19/07771 ,  Y10T428/24355 ,  Y10T428/32

摘要： A water-repelling layer is formed on a resin film, and a stripe pattern region is formed so as to be positioned within a surface region of the water-repelling layer and so as to be relatively hydrophilic with respect to water repellency of the water-repelling layer. A magnetic stripe pattern is formed of needle-shaped magnetic grains oriented and aggregated in the stripe pattern region. The needle-shaped magnetic grains are arranged in a desirable state in a predetermined stripe pattern, with a high magnetic permeability and a magnetic sheet with stripe-arranged magnetic grains that is thin and flexible is obtained.

摘要翻译： 在树脂膜上形成防水层，并且形成条纹图案区域，以便位于防水层的表面区域内，并且相对于水溶性防水层的防水性而相对亲水， 排斥层。 磁条图案由在条纹图案区域中定向和聚集的针状磁性颗粒形成。 针状磁性颗粒以预定的条纹图案被布置成期望的状态，具有高磁导率，并且获得薄且柔性的带状排列的磁性颗粒的磁性片。

公开(公告)号：US20090085227A1

公开(公告)日：2009-04-02

申请号：US11914581

申请日：2006-05-09

申请人： Tsukasa Shiraishi ,  Seiichi Nakatani ,  Seiji Karashima ,  Koichi Hirano ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Tsukasa Shiraishi ,  Seiichi Nakatani ,  Seiji Karashima ,  Koichi Hirano ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L21/563 ,  H01L23/552 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/83007 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/83136 ,  H01L2224/83139 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/83888 ,  H01L2224/9201 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/303 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10568 ,  H05K2201/10977 ,  H05K2201/2036 ,  H05K2203/083 ,  H05K2203/087 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/13111

摘要： A flip chip mounting body in which a circuit substrate having a plurality of connection terminals and an electronic part (semiconductor chip) having a plurality of electrode terminals are aligned face to face with each other, with a resin composition composed of solder powder, a resin and a convection additive being sandwiched in between, while a means such as spacers is interposed in between so as to provide a uniform gap between the two parts, or the electronic part (semiconductor chip) is placed inside a plate-shaped member having two or more protruding portions, so that the solder powder is allowed to move through boiling of the convection additive and to be self-aggregated to form a solder layer, thereby electrically connecting the connection terminals and the electrode terminals; and a mounting method for such a mounting body.

摘要翻译： 一种倒装芯片安装体，其中具有多个连接端子的电路基板和具有多个电极端子的电子部件（半导体芯片）彼此面对面地对准，其中树脂组合物由焊料粉末，树脂 并且夹在其间的对流添加剂，同时诸如间隔物的装置插入其间，以便在两个部件之间提供均匀的间隙，或者将电子部件（半导体芯片）放置在具有两个或 更多的突出部分，使得焊料粉末能够通过对流添加剂的沸腾而移动并且自聚集形成焊料层，从而电连接连接端子和电极端子; 以及这种安装体的安装方法。

公开(公告)号：US08709293B2

公开(公告)日：2014-04-29

申请号：US11793175

申请日：2005-12-14

申请人： Takashi Kitae ,  Seiji Karashima ,  Koichi Hirano ,  Toshiyuki Kojima ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita

发明人： Takashi Kitae ,  Seiji Karashima ,  Koichi Hirano ,  Toshiyuki Kojima ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita

IPC分类号： H01B1/02

CPC分类号： H05K3/323 ,  H01L21/6835 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/11001 ,  H01L2224/11003 ,  H01L2224/1141 ,  H01L2224/11502 ,  H01L2224/11522 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/165 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/293 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29316 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83097 ,  H01L2224/83192 ,  H01L2224/832 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/83886 ,  H01L2224/83887 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01061 ,  H01L2924/01065 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/083 ,  H05K2203/087 ,  Y02P70/613 ,  H01L2924/00011 ,  H01L2924/066 ,  H01L2924/06 ,  H01L2924/0695 ,  H01L2924/062 ,  H01L2924/0615 ,  H01L2924/068 ,  H01L2924/0705 ,  H01L2924/0675 ,  H01L2924/07001 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00014

摘要： There is provided a flip-chip mounting resin composition which can be used for a flip-chip mounting process that is high in productivity and reliability and thus can be applicable to a flip-chip mounting of a next-generation LSI. This flip-chip mounting resin composition comprises a resin, metal particles and a convection additive 12 that boils upon heating the resin 13. Upon the heating of the resin 13, the metal particles melt and the boiling convection additive 12 convects within the resin 13. This flip-chip mounting resin composition is supplied between a circuit substrate 10 and a semiconductor chip 20, and subsequently the resin 13 is heated so that the molten metal particles self-assemble into the region between each electrode of the circuit substrate and each electrode of the semiconductor chip. As a result, an electrical connection is formed between each electrode of the circuit substrate and each electrode of the semiconductor chip. Finally, the resin 13 is allowed to cure so that the semiconductor chip 20 is secured to the circuit substrate 10, which leads to in a formation of a flip chip assembly.

摘要翻译： 提供了一种倒装芯片安装树脂组合物，其可用于生产率和可靠性高的倒装芯片安装工艺，因此可以应用于下一代LSI的倒装芯片安装。 这种倒装芯片安装树脂组合物包括树脂，金属颗粒和在加热树脂13时沸腾的对流添加剂12.当加热树脂13时，金属颗粒熔化，沸腾对流添加剂12在树脂13内对流。 将该倒装芯片安装树脂组合物供给在电路基板10和半导体芯片20之间，随后加热树脂13，使得熔融金属颗粒自组装成电路基板的每个电极和电极的每个电极之间的区域 半导体芯片。 结果，在电路基板的每个电极和半导体芯片的每个电极之间形成电连接。 最后，使树脂13固化，使得半导体芯片20固定到电路基板10，这导致形成倒装芯片组件。

公开(公告)号：US07888789B2

公开(公告)日：2011-02-15

申请号：US11090401

申请日：2005-03-25

申请人： Yasuhiro Sugaya ,  Shingo Komatsu ,  Koichi Hirano ,  Seiichi Nakatani ,  Yasuyuki Matsuoka ,  Toshiyuki Asahi ,  Yoshihisa Yamashita

发明人： Yasuhiro Sugaya ,  Shingo Komatsu ,  Koichi Hirano ,  Seiichi Nakatani ,  Yasuyuki Matsuoka ,  Toshiyuki Asahi ,  Yoshihisa Yamashita

IPC分类号： H01L23/12 ,  H01L21/4763 ,  H01R43/20

CPC分类号： H05K3/20 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2924/0002 ,  H01L2924/0102 ,  H01L2924/01078 ,  H05K1/0306 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/205 ,  H05K3/4061 ,  H05K3/4069 ,  H05K2203/1461 ,  Y10T29/49149 ,  Y10T29/49179 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T428/12486 ,  H01L2924/00

摘要： A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.

摘要翻译： 能够可靠且容易地将精细布线图案转印到基板上的转印材料。 转印材料包括作为载体的第一金属层，作为布线图案转印到基板的第二金属层和可释放地粘附第一和第二金属层的剥离层的至少三层。 在第一金属层的表面部分上形成与布线图形对应的凹凸部分，并且在凸部的区域上形成剥离层和第二金属层。