公开(公告)号：US20150249045A1

公开(公告)日：2015-09-03

申请号：US14194502

申请日：2014-02-28

Applicant: Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

Inventor： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

IPC: H01L23/495 ,  H01L23/29 ,  H01L21/78

CPC classification number: H01L23/49551 ,  H01L21/561 ,  H01L21/78 ,  H01L23/043 ,  H01L23/24 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/73253

Abstract: A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units.

Abstract translation: 一种功率半导体器件的制备方法，包括：提供包含多个芯片安装单元的引线框架，每个芯片安装单元的模板的一个侧边缘向上弯曲并向上延伸，并且一个引线连接到所述芯片安装单元的弯曲侧边缘 模具桨，并且在与模桨相反的方向上延伸; 将半导体芯片附接到所述管芯焊盘的顶表面; 在半导体芯片的前面的每个电极上形成金属凸块，每个金属凸块的顶端从引线的顶表面的平面突出; 加热金属凸块并通过压板压制每个金属凸块的顶端，该压板形成与引线顶表面齐平的平坦顶端表面; 并切割引线框架以分离各个芯片安装单元。

公开(公告)号：US08981539B2

公开(公告)日：2015-03-17

申请号：US13913717

申请日：2013-06-10

Applicant: Yan Xun Xue ,  Hamza Yilmaz

Inventor： Yan Xun Xue ,  Hamza Yilmaz

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/34 ,  H01L23/12 ,  H01L23/02

CPC classification number: H01L23/49568 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/17 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.

Abstract translation: 功率半导体器件包括引线框单元，控制管芯，第一MOSFET管芯和第二MOSFET管芯，其中引线框架单元至少包括用于安装第一和第二MOSFET管芯的管芯焊盘，第一管脚和第二管脚 引脚，用于连接到第一和第二MOSFET管芯的顶部电极，第一行载体引脚和第二排载体引脚，分别与第一和第二引脚成对设置，用于控制管芯安装在其上。

公开(公告)号：US20140361419A1

公开(公告)日：2014-12-11

申请号：US13913717

申请日：2013-06-10

Applicant: Yan Xun Xue ,  Hamza Yilmaz

Inventor： Yan Xun Xue ,  Hamza Yilmaz

IPC: H01L23/495

CPC classification number: H01L23/49568 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/17 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.

Abstract translation: 功率半导体器件包括引线框单元，控制管芯，第一MOSFET管芯和第二MOSFET管芯，其中引线框架单元至少包括用于安装第一和第二MOSFET管芯的管芯焊盘，第一管脚和第二管脚 引脚，用于连接到第一和第二MOSFET管芯的顶部电极，第一行载体引脚和第二排载体引脚，分别与第一和第二引脚成对设置，用于控制管芯安装在其上。

公开(公告)号：US20140361418A1

公开(公告)日：2014-12-11

申请号：US13913183

申请日：2013-06-07

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

IPC: H01L23/495

CPC classification number: H01L23/4951 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

Abstract translation: 本发明涉及倒装芯片的半导体封装以及制造半导体封装的方法。 半导体芯片包括金属氧化物半导体场效应晶体管。 在包括第一基底，第二基底和第三基底的裸片上，在第一基底和第二基底的顶表面上进行半蚀刻或冲孔，以获得多个凹槽，该凹槽将第一基底 进入包括多个第一连接区域的多个区域，并且将第二基座的顶表面分成包括至少第二连接区域的多个区域。 半导体芯片在第一连接区域和第二连接区域处连接到管芯焊盘。

公开(公告)号：US08865523B2

公开(公告)日：2014-10-21

申请号：US13833341

申请日：2013-03-15

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC: H01L23/495 ,  H01L21/78

CPC classification number: H01L23/49562 ,  H01L21/561 ,  H01L21/78 ,  H01L23/06 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49568 ,  H01L2224/32245 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.

Abstract translation: 一种制造半导体封装器件的方法包括将引线框架安装在模制半导体芯片的底部，该底部具有覆盖半导体芯片的顶面的第一塑料封装体，用第二塑料封装体封装引线框和半导体芯片 导电接触体的顶表面电连接到半导体芯片的顶表面上的电极，并暴露在组件结构的顶表面上的导电焊盘，以通过导电接触体提供与电极的外部电连接。

公开(公告)号：US20140141567A1

公开(公告)日：2014-05-22

申请号：US13678847

申请日：2012-11-16

Applicant: Lei Shi ,  Yan Xun Xue ,  Yuping Gong

Inventor： Lei Shi ,  Yan Xun Xue ,  Yuping Gong

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L21/4832 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.

Abstract translation: 公开了专门用于倒装芯片垂直功率器件的封装半导体器件的制备方法。 在这些方法中，将垂直半导体芯片倒装芯片连接到引线框架，然后用塑料包装材料封装。 然后将封装的芯片变薄到预定厚度。 通过蚀刻至少连接的引线框架的底部部分，形成连接芯片与外部电路的接触端子。

公开(公告)号：US08716069B2

公开(公告)日：2014-05-06

申请号：US13631471

申请日：2012-09-28

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

IPC: H01L21/00 ,  H01R43/00 ,  H01L23/495 ,  H05K5/02

CPC classification number: H01L23/49861 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/49503 ,  H01L23/49562 ,  H01L23/49579 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  Y10T29/49121 ,  Y10T29/49172 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

Abstract translation: 半导体器件包括具有覆盖铝合金引线框架的暴露部分的钝化层的铝合金引线框架。 由于铝合金是低成本材料，其硬度和柔韧性适用于冲压，弯曲，成型等变形过程，铝合金引线框架适合批量生产; 此外，由于其重量比铜或铁镍材料低得多，因此铝合金引线框对于半导体器件的生产非常方便。

公开(公告)号：US20130210215A1

公开(公告)日：2013-08-15

申请号：US13396531

申请日：2012-02-14

Applicant: Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

Inventor： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

IPC: H01L21/78

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/94 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00015

Abstract: A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a centre area of the backside of the wafer after grinding the wafer backside to reduce the wafer thickness; detecting from the backside of the wafer sections of scribe lines formed in the front surface in the region between the edge of the metal layer and the edge of the wafer and cutting the wafer and the metal layer from the wafer backside along a straight line formed by extending a scribe line section detected from the wafer backside.

Abstract translation: 具有背面晶片切割的封装方法包括以下步骤：在晶片的前表面形成支撑结构，然后在晶片背面研磨之后在晶片背面的中心区域沉积金属层以减小晶片厚度; 从形成在金属层的边缘与晶片边缘之间的区域中的前表面的划线的背面检测，并从晶片背面沿着直线形成的直线切割晶片和金属层， 延伸从晶片背面检测的划线部分。

公开(公告)号：US20130134502A1

公开(公告)日：2013-05-30

申请号：US13750944

申请日：2013-01-25

Applicant: Yueh-Se Ho ,  Yan Xun Xue

Inventor： Yueh-Se Ho ,  Yan Xun Xue

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L23/485 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/03 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Abstract translation: 描述半导体器件，制造半导体器件的方法和电路封装组件。 半导体器件可以具有带有第一和第二表面的半导体衬底和它们之间的侧壁。 第一和第二表面上的第一和第二导电焊盘与衬底中对应的第一和第二半导体器件结构电接触。 第一表面和侧壁上的绝缘体层覆盖第一表面上的第一导电焊盘的一部分。 在第一导电焊盘和侧壁上的绝缘体层的一部分上的导电层与第二导电焊盘电接触。 绝缘体层防止导电层在第一和第二导电焊盘之间形成电接触。

公开(公告)号：US20130026615A1

公开(公告)日：2013-01-31

申请号：US13193474

申请日：2011-07-28

Applicant: Yuping Gong ,  Yan Xun Xue

Inventor： Yuping Gong ,  Yan Xun Xue

IPC: H01L21/60 ,  H01L23/495

CPC classification number: H01L23/49537 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49562 ,  H01L23/49568 ,  H01L2224/16245 ,  H01L2224/32245

Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.

Abstract translation: 双面露出的半导体器件包括安装在导热但不导电的第二引线框架的顶部的导电第一引线框架和翻转并附接在第一引线框架顶部上的半导体芯片。 翻转芯片顶部的栅极和源极电极分别与第一引线框架的栅极和源极引脚形成电连接。 第一和第二引线框架的翻转芯片和中心部分然后用模塑料封装，使得形成在第二引线框架的中心处的散热器和在半导体芯片的底部的漏电极暴露在两个相对的 半导体器件的侧面。 因此，在不增加半导体器件的尺寸的情况下，有效地提高了半导体器件的散热性能。