利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

43 条记录 (耗时 0.024 秒)

    Fully Integrated Organic Layered Processes for Making Plastic Electronics Based on Conductive Polymers and Semiconductor Nanowires
    21.
    发明申请
    Fully Integrated Organic Layered Processes for Making Plastic Electronics Based on Conductive Polymers and Semiconductor Nanowires 审中-公开
    基于导电聚合物和半导体纳米线制造塑料电子的全集成有机分层工艺

    公开(公告)号：US20080128688A1

    公开(公告)日：2008-06-05

    申请号：US12016701

    申请日：2008-01-18

    申请人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

    发明人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

    IPC分类号： H01L51/05

    CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

    摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

    摘要翻译： 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

    Selective processing of semiconductor nanowires by polarized visible radiation
    23.
    发明授权
    Selective processing of semiconductor nanowires by polarized visible radiation 有权
    通过极化可见辐射选择性处理半导体纳米线

    公开(公告)号：US07786024B2

    公开(公告)日：2010-08-31

    申请号：US11936590

    申请日：2007-11-07

    申请人： David P. Stumbo ,  Yaoling Pan ,  Costas P. Grigoropoulos ,  Nipun Misra

    发明人： David P. Stumbo ,  Yaoling Pan ,  Costas P. Grigoropoulos ,  Nipun Misra

    IPC分类号： H01L21/00

    CPC分类号： H01L29/0665 ,  B23K26/073 ,  B82Y10/00 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/0673 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods, systems, and apparatuses for annealing semiconductor nanowires and for fabricating electrical devices are provided. Nanowires are deposited on a substrate. A plurality of electrodes is formed. The nanowires are in electrical contact with the plurality of electrodes. The nanowires are doped. A polarized laser beam is applied to the nanowires to anneal at least a portion of the nanowires. The nanowires may be aligned substantially parallel to an axis. The laser beam may be polarized in various ways to modify absorption of radiation of the applied laser beam by the nanowires. For example, the laser beam may be polarized in a direction substantially parallel to the axis or substantially perpendicular to the axis to enable different nanowire absorption profiles.

    摘要翻译： 提供了用于退火半导体纳米线并用于制造电气器件的方法，系统和装置。 纳米线沉积在基底上。 形成多个电极。 纳米线与多个电极电接触。 纳米线是掺杂的。 将极化激光束施加到纳米线以退火至少一部分纳米线。 纳米线可以基本上平行于轴线对准。 激光束可以以各种方式被极化，以通过纳米线来改变施加的激光束的辐射的吸收。 例如，激光束可以在基本上平行于轴线或基本上垂直于轴线的方向上极化，以实现不同的纳米线吸收曲线。

    Gate configuration for nanowire electronic devices
    24.
    发明授权
    Gate configuration for nanowire electronic devices 失效
    纳米线电子器件的栅极配置

    公开(公告)号：US07473943B2

    公开(公告)日：2009-01-06

    申请号：US11233398

    申请日：2005-09-22

    申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

    发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

    IPC分类号： H01L29/80

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

    摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

    摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

    Efficient thermal activation optical switch and method of making the same
    27.
    发明授权
    Efficient thermal activation optical switch and method of making the same 有权
    高效热激活光开关及其制作方法

    公开(公告)号：US06678435B2

    公开(公告)日：2004-01-13

    申请号：US09861120

    申请日：2001-05-18

    申请人： Yaoling Pan ,  Michele Palmieri ,  Richard E. Haven

    发明人： Yaoling Pan ,  Michele Palmieri ,  Richard E. Haven

    IPC分类号： G02B626

    CPC分类号： G02B6/3576 ,  G02B6/3538 ,  G02B6/3546 ,  G02B2006/12145

    摘要： An optical switch having an insulator under a heater element is disclosed. The insulator reduces the heat loss thereby making the switch more efficient. The insulator is fabricated embedded in the underlying substrate on which the heater and the optical intersection are fabricated. A method of fabricating the optical switch having an insulator is disclosed. A trench is etched on the substrate and filled with oxide or other suitable insulating material. Then, the heater and the optical intersection are fabricated above the insulator.

    摘要翻译： 公开了一种在加热器元件下方具有绝缘体的光开关。 绝缘体减少热损失，从而使开关更有效率。 制造的绝缘体嵌入在其上制造加热器和光学交叉点的下面的基板上。 公开了一种制造具有绝缘体的光开关的方法。 在衬底上蚀刻沟槽，并填充有氧化物或其它合适的绝缘材料。 然后，在绝缘体上方制造加热器和光学交叉点。

    Thin film stack with surface-conditioning buffer layers and related methods
    29.
    发明授权
    Thin film stack with surface-conditioning buffer layers and related methods 有权
    具有表面调节缓冲层的薄膜叠层及相关方法

    公开(公告)号：US08817358B2

    公开(公告)日：2014-08-26

    申请号：US13565688

    申请日：2012-08-02

    申请人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

    发明人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

    IPC分类号： G02B26/00 ,  G02F1/03

    CPC分类号： G02B26/001

    摘要： This disclosure provides systems, methods and apparatus for a thin film stack with surface-conditioning buffer layers. In one aspect, the thin film stack includes a plurality of thin film layers each having a thickness greater than about 10 nm and a plurality of surface-conditioning buffer layers each having a thickness between about 1 nm and about 10 nm. The surface-conditioning buffer layers are alternatingly disposed between the thin film layers. Each of the surface-conditioning buffer layers are formed with the same or substantially the same thickness and composition. In some implementations, the surface-conditioning buffer layers are formed by atomic layer deposition.

    摘要翻译： 本公开提供了具有表面调节缓冲层的薄膜堆叠的系统，方法和装置。 在一个方面，薄膜堆叠包括多个厚度大于约10nm的薄膜层以及各自具有约1nm至约10nm厚度的多个表面调节缓冲层。 表面调节缓冲层交替地设置在薄膜层之间。 每个表面调节缓冲层以相同或基本上相同的厚度和组成形成。 在一些实施方案中，表面调节缓冲层通过原子层沉积形成。

    Amorphous oxide semiconductor thin film transistor fabrication method
    30.
    发明授权
    Amorphous oxide semiconductor thin film transistor fabrication method 有权
    无定形氧化物半导体薄膜晶体管制造方法

    公开(公告)号：US08797303B2

    公开(公告)日：2014-08-05

    申请号：US13052446

    申请日：2011-03-21

    申请人： Cheonhong Kim ,  John Hyunchul Hong ,  Yaoling Pan

    发明人： Cheonhong Kim ,  John Hyunchul Hong ,  Yaoling Pan

    IPC分类号： G09G5/00 ,  H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  G02B26/00

    CPC分类号： H01L29/66742 ,  G02B26/001 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78693

    摘要： This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source region, a drain region, and a channel region between the source region and the drain region is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel region, and a first metal layer on the dielectric layer. A second metal layer is formed on the oxide semiconductor layer overlying the source region and the drain region. The oxide semiconductor layer and the second metal layer are treated to form a heavily doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source region and the drain region. An oxide in the second metal layer also can be formed.

    摘要翻译： 本公开提供了用于制造薄膜晶体管器件的系统，方法和装置。 一方面，提供了在源极区域和漏极区域之间具有源极区域，漏极区域和沟道区域的衬底。 衬底还包括氧化物半导体层，覆盖沟道区的第一介电层和介电层上的第一金属层。 在覆盖源极区域和漏极区域的氧化物半导体层上形成第二金属层。 处理氧化物半导体层和第二金属层以在覆盖源极区和漏极区的氧化物半导体层中形成重掺杂的n型氧化物半导体。 也可以形成第二金属层中的氧化物。