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35 条记录 (耗时 0.027 秒)

    Balanced-to-unbalanced transformer embedded with filter
    23.
    发明授权
    Balanced-to-unbalanced transformer embedded with filter 失效
    平衡 - 不平衡变压器嵌入式滤波器

    公开(公告)号：US07471166B2

    公开(公告)日：2008-12-30

    申请号：US11633545

    申请日：2006-12-05

    申请人： Chang-Lin Wei ,  Chang-Sheng Chen ,  Syun Yu ,  Ying-Jiunn Lai ,  Uei-Ming Jow

    发明人： Chang-Lin Wei ,  Chang-Sheng Chen ,  Syun Yu ,  Ying-Jiunn Lai ,  Uei-Ming Jow

    IPC分类号： H01P5/10 ,  H01P1/20 ,  H01P1/203

    CPC分类号： H01P5/10

    摘要： A balanced-to-unbalanced transformer embedded with a filter, the balanced-to-unbalanced transformer being disposed in a multi-layered substrate and comprising vertically coupled transmission lines designed in different layers in the multi-layer substrate to increase transmission performances. A capacitor and a transmission line are connected to a single-ended I/O port of the balanced-to-unbalanced transformer such that a filter is embedded in the balanced-to-unbalanced transformer.

    摘要翻译： 一种嵌入滤波器的平衡不平衡变压器，平衡不平衡变压器设置在多层衬底中，并且包括在多层衬底中以不同层设计的垂直耦合传输线，以增加传输性能。 电容器和传输线连接到平衡不平衡变压器的单端I / O端口，使得滤波器嵌入在平衡不平衡变压器中。

    Multi-layered printed circuit board embedded with filter
    24.
    发明申请
    Multi-layered printed circuit board embedded with filter 失效
    多层印刷电路板嵌入式滤波器

    公开(公告)号：US20070133182A1

    公开(公告)日：2007-06-14

    申请号：US11438363

    申请日：2006-05-23

    申请人： Chang-Sheng Chen ,  Uei-Ming Jow ,  Ying-Jiunn Lai ,  Chin-Sun Shyu

    发明人： Chang-Sheng Chen ,  Uei-Ming Jow ,  Ying-Jiunn Lai ,  Chin-Sun Shyu

    IPC分类号： H05K7/00

    CPC分类号： H05K1/162 ,  H03H7/09 ,  H03H7/1775 ,  H03H2001/0085 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/09236 ,  H05K2201/09672

    摘要： A multi-layered printed circuit board embedded with a filter, the multi-layered printed circuit board using a composite multi-layered printed circuit board formed of at least a high dielectric material stacked with at least a low dielectric material. A plurality of serial or parallel capacitors are disposed in the composite multi-layered printed circuit board so as to form a filter. At least one capacitor is an interdigital capacitor disposed on a low dielectric material. Metal electrodes of the interdigital capacitor are located on the same plane such that the area of the metal electrodes or the spacing between the metal electrodes can be adjusted in advance to precisely control the electrical properties such as the center frequency and the transmission loss of the filter. Problems resulting from alignment errors caused in manufacturing the composite multi-layered printed circuit board can also be prevented.

    摘要翻译： 嵌入滤光器的多层印刷电路板，使用由至少由至少低介电材料层叠的高介电材料形成的复合多层印刷电路板的多层印刷电路板。 多个串联或并联电容器设置在复合多层印刷电路板中以形成滤波器。 至少一个电容器是设置在低电介质材料上的叉指电容器。 叉指电容器的金属电极位于同一平面上，使得金属电极的面积或金属电极之间的间隔可以预先调整以精确地控制诸如滤波器的中心频率和传输损耗之类的电气特性 。 也可以防止在制造复合多层印刷电路板时引起的对准误差所引起的问题。

    Embedded microelectronic capacitor incorporating ground shielding layers and method for fabrication
    26.
    发明授权
    Embedded microelectronic capacitor incorporating ground shielding layers and method for fabrication 有权
    具有接地屏蔽层的嵌入式微电子电容器及其制造方法

    公开(公告)号：US06969912B2

    公开(公告)日：2005-11-29

    申请号：US10713804

    申请日：2003-11-14

    申请人： Uei-Ming Jow ,  Pei-Shen Wei ,  Ching-Liang Weng ,  Chun-Kun Wu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

    发明人： Uei-Ming Jow ,  Pei-Shen Wei ,  Ching-Liang Weng ,  Chun-Kun Wu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

    IPC分类号： H01L21/4763 ,  H01L23/053 ,  H01L23/48 ,  H05K1/02 ,  H05K1/16 ,  H05K3/46

    CPC分类号： H05K1/162 ,  H05K1/0218 ,  H05K1/0219 ,  H05K3/4602 ,  H05K2201/0723 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09672

    摘要： An embedded microelectronic capacitor incorporating at least one ground shielding layer is provided which includes an upper ground shielding layer that has an aperture therethrough; an electrode plate positioned spaced-apart from the upper ground shielding layer that has a via extending upwardly away from the electrode plate through the aperture in the upper ground shielding layer providing electrical communication to the electrode plate without shorting to the upper ground shielding layer; a middle ground shielding layer positioned in the same plane of the electrode plate, surrounding while spaced-apart from the electrode plate at a predetermined distance; a lower ground shielding layer positioned spaced-apart from the electrode plate in an opposing relationship to the upper ground shielding layer; and a dielectric material embedding the upper ground shielding layer; the middle ground shielding layer and the lower ground shielding layer.

    摘要翻译： 提供了包括至少一个接地屏蔽层的嵌入式微电子电容器，其包括具有穿过其中的孔的上接地屏蔽层; 与所述上接地屏蔽层间隔开的电极板，所述电极板具有通过所述上接地屏蔽层中的孔向上远离所述电极板延伸的通孔，所述通孔提供与所述电极板的电连通而不与所述上接地屏蔽层短路; 位于电极板的同一平面中的中间屏蔽层，以与预定距离的电极板隔开间隔开; 与所述上接地屏蔽层相对的位置与所述电极板隔开定位的下接地屏蔽层; 以及嵌入上接地屏蔽层的电介质材料; 中间接地屏蔽层和下部接地屏蔽层。

    INTEGRATED CIRCUIT
    27.
    发明申请
    INTEGRATED CIRCUIT 审中-公开
    集成电路

    公开(公告)号：US20150271914A1

    公开(公告)日：2015-09-24

    申请号：US14274784

    申请日：2014-05-12

    申请人： Ying-Jiunn Lai ,  Jung-Chi Ho

    发明人： Ying-Jiunn Lai ,  Jung-Chi Ho

    IPC分类号： H05K1/02 ,  H05K1/11

    CPC分类号： H01L23/58 ,  H01L23/50 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/647 ,  H01L23/66 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49175 ,  H04L25/00 ,  H01L2924/00014

    摘要： An integrated circuit (IC) is provided. The IC includes a chip/die and a package. The chip/die includes a first bonding pad, a second bonding pad, a core circuit and a resistance unit. The first bonding pad is coupled to a signal path of the core circuit. The two ends of the resistance unit are respectively coupled to the first bonding pad and the second bonding pad. The package includes a pin and a low-pass circuit. The pin is electrically connected to the first bonding pad. The low-pass circuit is electrically connected to the second bonding pad.

    摘要翻译： 提供集成电路（IC）。 IC包括芯片/管芯和封装。 芯片/裸片包括第一焊盘，第二焊盘，芯电路和电阻单元。 第一焊盘耦合到核心电路的信号路径。 电阻单元的两端分别耦合到第一焊盘和第二接合焊盘。 封装包括一个引脚和一个低通电路。 引脚电连接到第一焊盘。 低通电路电连接到第二接合焊盘。

    Complementary mirror image embedded planar resistor architecture
    29.
    发明授权
    Complementary mirror image embedded planar resistor architecture 有权
    互补镜像嵌入式平面电阻架构

    公开(公告)号：US08035036B2

    公开(公告)日：2011-10-11

    申请号：US11861297

    申请日：2007-09-26

    申请人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

    发明人： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

    IPC分类号： H05K1/16

    CPC分类号： H05K1/167 ,  H05K1/0224 ,  H05K1/025 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/09681 ,  H05K2201/0969

    摘要： A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

    摘要翻译： 提供了一种互补镜像嵌入式平面电阻架构。 在该结构中，在接地平面或电极平面上形成互补的中空结构以最小化寄生电阻，从而有效地提高施加频率。 此外，在某些情况下，一些信号传输线通过嵌入式平面电阻器下方的位置，如果根本没有屏蔽，则会发生严重的干扰或串扰现象。 因此，将接地平面，电极平面或与嵌入式平面电阻器相邻的功率层的互补空心结构设计为网格结构，以减少干扰或串扰现象。 以这种方式，整个电阻器结构在电路中具有优选的高频电特性。