公开(公告)号：US09515613B2

公开(公告)日：2016-12-06

申请号：US14573669

申请日：2014-12-17

Applicant: Abdulrhman M. S. Ahmed ,  Ramanujam Srinidhi Embar ,  Yu-Ting D Wu

Inventor： Abdulrhman M. S. Ahmed ,  Ramanujam Srinidhi Embar ,  Yu-Ting D Wu

IPC: H03F3/68 ,  H03F1/02 ,  H03F1/56 ,  H03F3/195

CPC classification number: H03F1/0288 ,  H03F1/0266 ,  H03F1/565 ,  H03F3/195 ,  H03F2200/111 ,  H03F2200/222 ,  H03F2200/423 ,  H03F2200/451

Abstract: A dual-band Doherty amplifier and method therefor are provided. The dual-band Doherty amplifier includes a first amplifier gain element, a first transmission line coupled to a first output of the first amplifier gain element, a second amplifier gain element, a second transmission line coupled to a second output of the second amplifier gain element, and a controller configured, when a signal to be amplified is in a first band, to provide a first bias signal to a first bias input of the first amplifier gain element and a second bias signal to a second bias input of the second amplifier gain element and, when the signal is in a second band, to provide the second bias signal to the first bias input of the first amplifier gain element and the first bias signal to the second bias input of the second amplifier gain element.

Abstract translation: 提供了一种双频带Doherty放大器及其方法。 双频带Doherty放大器包括第一放大器增益元件，耦合到第一放大器增益元件的第一输出端的第一传输线，第二放大器增益元件，耦合到第二放大器增益元件的第二输出的第二传输线 以及控制器，当待放大的信号处于第一频带时，将第一偏置信号提供给第一放大器增益元件的第一偏置输入，并将第二偏置信号提供给第二放大器增益的第二偏置输入 并且当信号处于第二频带时，将第二偏置信号提供给第一放大器增益元件的第一偏置输入并将第一偏置信号提供给第二放大器增益元件的第二偏置输入。

公开(公告)号：US09510200B2

公开(公告)日：2016-11-29

申请号：US14233185

申请日：2011-08-09

Applicant: Michael Priel ,  Evgeny Margolis ,  Anton Rozen

Inventor： Michael Priel ,  Evgeny Margolis ,  Anton Rozen

IPC: H04W12/08 ,  G06F21/10 ,  G06F21/55 ,  G06F21/81 ,  G06F1/32

CPC classification number: H04W12/08 ,  G06F1/3237 ,  G06F1/3287 ,  G06F1/3296 ,  G06F21/10 ,  G06F21/554 ,  G06F21/81 ,  G06F2221/2105 ,  G06F2221/2141 ,  Y02D10/171

Abstract: An electronic device comprises a secured module arranged to store secured data. A component outside the secured module has a normal operating mode with a normal mode operating voltage. An interface is arranged to provide access to the secured module. A voltage monitoring unit is connected to the component and arranged to monitor an operating voltage Vsup of the component. An interface control unit is connected to the voltage monitoring unit and the interface. The interface control unit is arranged to inhibit access to the secured module through the interface when the operating voltage is below a predetermined secure access voltage level, the secure access voltage being higher than the normal mode operating voltage.

Abstract translation: 电子设备包括被安排为存储安全数据的安全模块。 安全模块外部的组件具有正常工作模式，具有正常模式工作电压。 布置了一个接口来提供对安全模块的访问。 电压监视单元连接到部件并且被布置成监视部件的工作电压Vsup。 接口控制单元连接到电压监视单元和接口。 接口控制单元被布置成当工作电压低于预定安全存取电压电平时，通过接口禁止对安全模块的访问，安全访问电压高于正常模式工作电压。

公开(公告)号：US09508845B1

公开(公告)日：2016-11-29

申请号：US14822122

申请日：2015-08-10

Applicant: Freescale Semiconductor, Inc.

Inventor： Xin Lin ,  Hongning Yang ,  Jiang-Kai Zuo

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/66659 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7835

Abstract: An LDMOS device implements a substrate having a buried isolation layer, a first well region that incorporates two stacked sub-regions to provide a PN junction with a RESURF effect, and a second well region laterally offset from the first well region. A source region is formed in one of the well regions and a drain region is formed in the other well region. An extension region is disposed immediately adjacent to the first well region and laterally distal to the second well region. An extension biasing region is formed at least partially within the extension region, and is separated from the first well region by a portion of the extension region. One or more metallization structures electrically couple the extension biasing region to the one of the source/drain region in the second well region. A gate structure at least partially overlaps both well regions.

Abstract translation: LDMOS器件实现具有掩埋隔离层的衬底，第一阱区域，其结合两个堆叠的子区域以提供具有RESURF效应的PN结，以及从第一阱区域横向偏移的第二阱区域。 在一个阱区中形成源极区，在另一个阱区中形成漏极区。 延伸区域紧邻第一井区域并且横向于第二井区域的横向设置。 延伸偏置区域至少部分地形成在延伸区域内，并且通过延伸区域的一部分与第一阱区域分离。 一个或多个金属化结构将延伸偏置区域电耦合到第二阱区域中的源极/漏极区域中的一个。 门结构至少部分地重叠两个阱区。

公开(公告)号：US09508701B2

公开(公告)日：2016-11-29

申请号：US14039622

申请日：2013-09-27

Applicant: Freescale Semiconductor, Inc.

Inventor： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/304 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/0569 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/1414 ,  H01L2224/14517 ,  H01L2224/16111 ,  H01L2224/16147 ,  H01L2224/48463 ,  H01L2224/73257 ,  H01L2224/8114 ,  H01L2224/81815 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/384 ,  H01L2924/00 ,  H01L2224/03 ,  H01L21/78 ,  H01L21/56 ,  H01L2224/81 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for 3D device packaging utilizes through-substrate pillars to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second die includes a set of metal pillars. The first die and the second die are stacked such that each metal pillar extends from a surface of the second die to a corresponding pad via a corresponding access hole. The first die and second die are mechanically and electrically bonded via solder joints formed between the metal pillars and the corresponding pads.

Abstract translation: 用于3D设备封装的方法利用贯穿基板支柱将两个或更多个骰子机械地和电气地接合。 第一管芯包括从第一管芯的表面延伸到第一管芯的金属层处的一组焊盘的一组入口孔。 第二个模具包括一套金属支柱。 第一管芯和第二管芯被堆叠成使得每个金属柱经由相应的通孔从第二管芯的表面延伸到相应的焊盘。 第一模具和第二模具通过形成在金属柱和相应焊盘之间的焊接点机械地和电连接。

公开(公告)号：US09508397B1

公开(公告)日：2016-11-29

申请号：US14957778

申请日：2015-12-03

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Richard K. Eguchi ,  Thomas Jew ,  Craig T. Swift

IPC: G11C16/10 ,  G11C5/14 ,  G11C7/06

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/28 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004 ,  G11C2029/0409

Abstract: An operating voltage and reference current are adjusted in a memory device. At least a portion of an array of memory cells is preconditioned to an erased state using an erase verify voltage on word lines coupled to the memory cells and a first reference current in sense amplifiers coupled to bit lines for the array. A test reference current is set for the sense amplifiers. A bitcell gate voltage is set on the word lines to a present overdrive voltage. The at least a portion of the array is read. If any of the memory cells in the at least a portion of the array are read as being programmed, the present overdrive voltage is increased until none of the memory cells in the at least a portion of the array are read as being programmed.

Abstract translation: 在存储器件中调节工作电压和参考电流。 使用耦合到存储器单元的字线上的擦除验证电压和耦合到阵列的位线的读出放大器中的第一参考电流，将存储器单元阵列的至少一部分预处理为擦除状态。 为读出放大器设置测试参考电流。 字元栅极电压在字线上设置为当前的过驱动电压。 读取阵列的至少一部分。 如果阵列的至少一部分中的任何存储器单元被读取为被编程，则增加当前的过驱动电压，直到阵列的至少一部分中的存储单元都不被读取为被编程为止。

公开(公告)号：US09506756B2

公开(公告)日：2016-11-29

申请号：US13833290

申请日：2013-03-15

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Andrew C. McNeil ,  Yizhen Lin

IPC: G01C19/00 ,  G01C19/5712

CPC classification number: G01C19/5712

Abstract: A microelectromechanical systems (MEMS) device includes at least two rate sensors (20, 50) suspended above a substrate (30), and configured to oscillate parallel to a surface (40) of the substrate (30). Drive elements (156, 158) in communication with at least one of the rate sensors (20, 50) provide a drive signal (168) exhibiting a drive frequency. One or more coupling spring structures (80, 92, 104, 120) interconnect the rate sensors (20, 50). The coupling spring structures enable oscillation of the rate sensors (20, 50) in a drive direction dictated by the coupling spring structures. The drive direction for the rate sensors (20) is a rotational drive direction (43) associated with a first axis (28), and the drive direction for the rate sensors (50) is a translational drive direction (64) associated with a second axis (24, 26) that is perpendicular to the first axis (28).

Abstract translation: 微机电系统（MEMS）装置包括悬置在衬底（30）上方的至少两个速率传感器（20,50），并且被配置为平行于衬底（30）的表面（40）振荡。 与速率传感器（20,50）中的至少一个通信的驱动元件（156,158）提供具有驱动频率的驱动信号（168）。 一个或多个耦合弹簧结构（80,92,104,120）互连速率传感器（20,50）。 联接弹簧结构使得速率传感器（20,50）在联接弹簧结构所规定的驱动方向上能够振荡。 速率传感器（20）的驱动方向是与第一轴线（28）相关联的旋转驱动方向（43），速率传感器（50）的驱动方向是与第二轴线（28）相关联的平移驱动方向 轴线（24,26），其垂直于第一轴线（28）。

公开(公告)号：US09501443B2

公开(公告)日：2016-11-22

申请号：US14403607

申请日：2012-06-27

Applicant: Matthijs Pardoen

Inventor： Matthijs Pardoen

IPC: H03B1/00 ,  H03K3/00 ,  G06F13/40

CPC classification number: G06F13/4072

Abstract: A differential line driver circuit comprising a plurality of driver stages is described. Each driver stage is operably coupled to at least one output of the line driver circuit and arranged to receive at least one control signal and to drive at least one output signal on the at least one output of the line driver circuit in accordance with the at least one control signal received thereby. The line driver circuit further comprises at least one delay component arranged to receive the at least one control signal, and to sequentially propagate the at least one control signal to the driver stages with time delays between the propagation of the at least one control signal to sequentially adjacent driver stages. The delay component is arranged to sequentially propagate the at least one control signal to the driver stages such that such that the at least one control signal is propagated with at least one of: a progressively increasing time delay between sequentially adjacent driver stages; and a progressively decreasing time delay between sequentially adjacent driver stages.

Abstract translation: 描述了包括多个驱动器级的差分线路驱动器电路。 每个驱动器级可操作地耦合到线路驱动器电路的至少一个输出，并且被布置为接收至少一个控制信号，并且至少根据至少一个驱动器电路驱动线驱动器电路的至少一个输出上的至少一个输出信号 由此接收一个控制信号。 线路驱动器电路还包括布置成接收至少一个控制信号的至少一个延迟部件，并且将至少一个控制信号顺序地传播到驱动器级，在至少一个控制信号传播到顺序之间具有时间延迟 相邻的驾驶员阶段。 延迟分量被布置为将至少一个控制信号顺序地传播到驱动器级，使得至少一个控制信号以下列中的至少一个传播：在顺序相邻的驱动级之间逐渐增加的时间延迟; 并且在顺序相邻的驾驶员阶段之间逐渐减小时间延迟。

公开(公告)号：US20160336903A1

公开(公告)日：2016-11-17

申请号：US14714036

申请日：2015-05-15

Applicant: Maruf Ahmed ,  Joseph Staudinger

Inventor： Maruf Ahmed ,  Joseph Staudinger

IPC: H03F1/02 ,  H03F3/21 ,  H03F3/19

CPC classification number: H03F1/0288 ,  H03F1/565 ,  H03F3/19 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/171 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/451 ,  H03F2203/21106

Abstract: In various embodiments, a semiconductor package includes a carrier amplifier connected to a first output of a power divider, and a first output matching network connected to the carrier amplifier and an output combining node. The first output matching network exhibits a phase delay during operation of the carrier amplifier. The semiconductor package includes a phase advance network connected to the first output matching network. The phase advance network is configured to offset at least a portion of the phase delay of the first output matching network. The semiconductor package includes a peaking amplifier connected to a second output of the power divider and the output combining node, and a second output matching network connected to the peaking amplifier.

Abstract translation: 在各种实施例中，半导体封装包括连接到功率分配器的第一输出的载波放大器和连接到载波放大器的第一输出匹配网络和输出组合节点。 第一输出匹配网络在载波放大器的工作期间呈现相位延迟。 半导体封装包括连接到第一输出匹配网络的相位提前网络。 相位提前网络被配置为抵消第一输出匹配网络的相位延迟的至少一部分。 半导体封装包括连接到功率分配器和输出组合节点的第二输出的峰化放大器，以及连接到峰值放大器的第二输出匹配网络。

公开(公告)号：US09494969B2

公开(公告)日：2016-11-15

申请号：US14457133

申请日：2014-08-12

Applicant: Aniruddha Gupta ,  Akshay K. Pathak ,  Garima Sharda ,  Nidhi Sinha

Inventor： Aniruddha Gupta ,  Akshay K. Pathak ,  Garima Sharda ,  Nidhi Sinha

IPC: H03L7/00 ,  G06F1/12

CPC classification number: G06F1/12 ,  G06F1/08 ,  G06F1/24

Abstract: An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.

Abstract translation: 用于片上系统（SOC）的板上复位电路解决了当不同的电源域或复位域从不同的源接收复位时出现的异步复位时触发器的元稳定性问题。 为了改善这个问题，在时钟门控时，复位信号被断言和解除断言。 在断言（或解除断言）之后，重新设置时钟的最小时间，以便具有同步复位的逻辑也可以接收复位。

公开(公告)号：US09490243B2

公开(公告)日：2016-11-08

申请号：US14419064

申请日：2012-08-22

Applicant: Jean Philippe Laine ,  Patrice Besse

Inventor： Jean Philippe Laine ,  Patrice Besse

IPC: H01L27/02 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L27/0259 ,  H01L21/8222 ,  H01L27/0255 ,  H01L27/0647 ,  H01L29/0649 ,  H01L29/1095

Abstract: A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The p-dopant concentration of the two-doped region is higher than the p-dopant concentration of the isolated p-doped region. A first electrical contact is connected only via a highly doped p-contact region to the first p-doped region and a second electrical contact is connected only via another highly doped p-contact region to the second p-doped region.

Abstract translation: 提供一种包括ESD保护装置的半导体器件。 ESD保护器件由存在于半导体器件的结构中的一个或多个pnp晶体管形成。 半导体器件包括由N掺杂区域分离的隔离p掺杂区域的两个部分。 在两个部分内设置两个p掺杂区域。 双掺杂区域的p掺杂剂浓度高于分离的p掺杂区域的p掺杂剂浓度。 第一电接触仅通过高度掺杂的p接触区域连接到第一p掺杂区域，并且第二电触点仅通过另一个高度掺杂的p接触区域连接到第二p掺杂区域。