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106 条记录 (耗时 0.043 秒)

    Energy Extraction From The Parasitic Elements In Power Converters
    23.
    发明公开
    Energy Extraction From The Parasitic Elements In Power Converters 审中-公开

    公开(公告)号：US20240250602A1

    公开(公告)日：2024-07-25

    申请号：US18596214

    申请日：2024-03-05

    申请人： Rompower Technology Holdings, LLC

    发明人： Ionel Jitaru

    IPC分类号： H02M1/08 ,  H01F38/42 ,  H02M1/00 ,  H02M1/34 ,  H02M1/42 ,  H02M3/155 ,  H02M3/335

    CPC分类号： H02M1/083 ,  H02M1/4258 ,  H02M3/155 ,  H02M3/335 ,  H02M3/33553 ,  H02M3/33592 ,  H01F38/42 ,  H02M1/0058 ,  H02M1/342 ,  Y02B70/10

    摘要： A switching power conversion apparatus for converting power from an input voltage source to a load includes first and second switches connected to a switching node. An inductive element has a magnetizing current connected to the node, and the inductive element is connected to deliver energy via the first and second switches from the input voltage to the load during a succession of power conversion cycles. A capacitance connected to the node resonates with the inductive element to cause parasitic oscillation. A clamp subcircuit across the inductive element contains an auxiliary switch to trap energy and prevent parasitic oscillation, wherein the auxiliary switch is complementary to the first switch. A controlled voltage source injects energy in the inductive element, when the auxiliary switch turns off to discharge the parasitic capacitance by using trapped energy in the inductive element in addition to injected energy from the controlled voltage source.

    Interface clock management
    24.
    发明授权
    Interface clock management 有权

    公开(公告)号：US12032508B2

    公开(公告)日：2024-07-09

    申请号：US18144349

    申请日：2023-05-08

    申请人： Rambus Inc.

    发明人： Yuanlong Wang

    IPC分类号： G06F13/42 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237

    CPC分类号： G06F13/4243 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3275 ,  Y02B70/10 ,  Y02D10/00 ,  Y02D30/50

    摘要： The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

    Fault tolerant power converter
    25.
    发明授权
    Fault tolerant power converter 有权

    公开(公告)号：US11990848B1

    公开(公告)日：2024-05-21

    申请号：US18124862

    申请日：2023-03-22

    申请人： Vicor Corporation

    发明人： Patrizio Vinciarelli

    IPC分类号： H02M1/32 ,  H02M1/38 ,  H02M3/00 ,  H02M3/335 ,  H02M7/00 ,  H02M7/219 ,  H03K17/06 ,  H03K17/30 ,  H03K17/687 ,  H02M1/00

    CPC分类号： H02M7/219 ,  H02M1/32 ,  H02M1/38 ,  H02M3/01 ,  H02M3/33507 ,  H02M3/33576 ,  H02M7/003 ,  H03K17/063 ,  H03K17/302 ,  H03K17/6871 ,  H02M1/0032 ,  H02M1/325 ,  Y02B70/10

    摘要： A power converter provides a low-voltage output using a full-bridge fault-tolerant rectification circuit. The output circuit uses controlled switches as rectifiers. A fault detection circuit monitors circuit conditions. Upon detection of a fault, the switches are disabled decoupling the power converter from the system.
    A common-source dual MOSFET device includes a plurality of elements arranged in alternating patterns on a semiconductor die. A common-source dual synchronous rectifier includes control circuitry powered from the drain to source voltage of the complementary switch.
    A DC-to-DC transformer converts power from an input source to a load using a fixed voltage transformation ratio. A clamp phase may be used to reduce power losses in the converter at light loads, control the effective output resistance of the converter, effectively regulate the voltage transformation ratio, provide narrow band output regulation, and control the rate of change of output voltage for example during start up. One or more of the transformer windings may be clamped. The converter may use the sine amplitude converter topology. The converter may use common-source dual MOSFET devices and fault detection.
    The density of point of load power conversion may be increased and the associated power dissipation reduced by removing the input driver circuitry from the point of load where it is not necessary. An output circuit may be located at the point of load providing fault tolerant rectification of the AC power from the secondary winding of a power transformer which may be located nearby the output circuit. The resonant voltage and current waveforms on the primary side of the transformer are readily communicated via an AC bus between the driver circuit and the primary winding of the power transformer. The driver circuit may drive a plurality of transformer-output circuit pairs. The transformer and output circuit may be combined in a single module at the point of load. Alternatively, the output circuit may be integrated into point of load circuitry such as a processor core. The transformer may be deployed near the output circuit.

    INTERFACE CLOCK MANAGEMENT
    30.
    发明公开
    INTERFACE CLOCK MANAGEMENT 审中-公开

    公开(公告)号：US20230350835A1

    公开(公告)日：2023-11-02

    申请号：US18144349

    申请日：2023-05-08

    申请人： Rambus Inc.

    发明人： Yuanlong WANG

    IPC分类号： G06F13/42 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237

    CPC分类号： G06F13/4243 ,  G06F1/3206 ,  G06F1/3275 ,  G06F1/3237 ,  Y02D30/50 ,  Y02B70/10 ,  Y02D10/00

    摘要： The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.