公开(公告)号：US4314359A

公开(公告)日：1982-02-02

申请号：US157156

申请日：1980-06-06

申请人： Yukio Kato ,  Atsuo Hotta ,  Teruo Isobe

发明人： Yukio Kato ,  Atsuo Hotta ,  Teruo Isobe

IPC分类号： H01L21/74 ,  G11C11/411 ,  G11C11/414 ,  H01L21/316 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8229 ,  H01L27/04 ,  H01L27/07 ,  H01L27/102 ,  H01L29/73 ,  G11C11/40

CPC分类号： G11C11/414 ,  G11C11/4116 ,  H01L27/0755 ,  H01L27/1025 ,  Y10S438/901

摘要： The invention relates to an improvement in a semiconductor memory device including flip-flop type memory cells, each memory cell consisting of a pair of cross-coupled multi-emitter transistors. The semiconductor memory device of the invention is characterized by including a capacitance added between the collector region and the base region of each of the transistor pair of each memory cell in order to prevent the memory cell from erroneously operating due to .alpha.-rays.

摘要翻译： 本发明涉及包括触发型存储单元的半导体存储器件的改进，每个存储器单元由一对交叉耦合多发射极晶体管组成。 本发明的半导体存储器件的特征在于，在每个存储单元的晶体管对的集电极区域和基极区域之间添加电容，以防止存储器单元由于α射线而被错误地操作。

公开(公告)号：US3441815A

公开(公告)日：1969-04-29

申请号：US3441815D

申请日：1966-09-14

申请人： WESTINGHOUSE ELECTRIC CORP

发明人： POLLOCK LARRY J ,  SHAUNFIELD WALLACE N

IPC分类号： H01L21/8222 ,  H01L27/06 ,  H01L29/00 ,  H01L19/00 ,  H01L11/06

CPC分类号： H01L27/0664 ,  H01L21/8222 ,  H01L27/0652 ,  H01L29/00 ,  Y10S148/037 ,  Y10S148/05 ,  Y10S148/062 ,  Y10S148/085 ,  Y10S438/901

公开(公告)号：US07781284B2

公开(公告)日：2010-08-24

申请号：US12706527

申请日：2010-02-16

申请人： Naoya Sashida

发明人： Naoya Sashida

IPC分类号： H01L21/8242 ,  H01L21/8234

CPC分类号： H01L27/11502 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/31612 ,  H01L27/105 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/40 ,  H01L28/55 ,  H01L28/65 ,  Y10S438/901

摘要： There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.

摘要翻译： 提供了一种半导体器件，其包括在硅（半导体）衬底上形成的第一层间绝缘膜（第一绝缘膜），形成在第一层间绝缘膜上并具有下电极，电介质膜和上电极的电容器 形成在所述电容器和所述第一层间绝缘膜上的第四层间绝缘膜（第二绝缘膜）以及形成在所述电容器及其周边上的所述第四层间绝缘膜上的金属图案，以具有与所述第四绝缘膜相反的方向的应力 层间绝缘膜。 结果，可以提高用层间绝缘膜覆盖的电容器的特性。

公开(公告)号：US07476921B2

公开(公告)日：2009-01-13

申请号：US11898960

申请日：2007-09-18

申请人： Naoya Sashida

发明人： Naoya Sashida

IPC分类号： H01L27/108

CPC分类号： H01L27/11502 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/31612 ,  H01L27/105 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/40 ,  H01L28/55 ,  H01L28/65 ,  Y10S438/901

摘要： There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.

摘要翻译： 提供了一种半导体器件，其包括在硅（半导体）衬底上形成的第一层间绝缘膜（第一绝缘膜），形成在第一层间绝缘膜上并具有下电极，电介质膜和上电极的电容器 形成在所述电容器和所述第一层间绝缘膜上的第四层间绝缘膜（第二绝缘膜）以及形成在所述电容器及其周边上的所述第四层间绝缘膜上的金属图案，以具有与所述第四绝缘膜相反的方向的应力 层间绝缘膜。 结果，可以提高用层间绝缘膜覆盖的电容器的特性。

公开(公告)号：US07176079B2

公开(公告)日：2007-02-13

申请号：US09912558

申请日：2001-07-26

申请人： Ronald A. Weimer ,  Scott J. DeBoer ,  Dan Gealy ,  Husam N. Al-Shareef

发明人： Ronald A. Weimer ,  Scott J. DeBoer ,  Dan Gealy ,  Husam N. Al-Shareef

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/3105 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/901

摘要： A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

摘要翻译： 制造半导体器件的方法包括沉积电介质膜并在快速热处理室中对电介质膜进行湿氧化。 该技术可以用于例如在集成电路中形成各种元件，包括栅介质膜以及电容元件。 通过RTP工艺提供的紧密温度控制允许快速进行湿氧化，使得氧化物质不会通过电介质膜显着扩散并扩散到下层。 在电容元件的情况下，该技术还可以有助于降低电介质膜的漏电流，而不会显着降低其电容。

公开(公告)号：US07022623B2

公开(公告)日：2006-04-04

申请号：US09296835

申请日：1999-04-22

申请人： Ronald A. Weimer ,  Scott J. DeBoer ,  Dan Gealy ,  Husam N. Al-Shareef

发明人： Ronald A. Weimer ,  Scott J. DeBoer ,  Dan Gealy ,  Husam N. Al-Shareef

IPC分类号： H01L21/00

CPC分类号： H01L21/3105 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/901

摘要： A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

摘要翻译： 制造半导体器件的方法包括沉积电介质膜并使电介质膜在快速热处理室中进行湿氧化。 该技术可以用于例如在集成电路中形成各种元件，包括栅介质膜以及电容元件。 通过RTP工艺提供的紧密温度控制允许快速进行湿氧化，使得氧化物质不会通过电介质膜显着扩散并扩散到下层。 在电容元件的情况下，该技术还可以有助于降低电介质膜的漏电流，而不会显着降低其电容。

公开(公告)号：US20050048793A1

公开(公告)日：2005-03-03

申请号：US10640309

申请日：2003-08-14

申请人： Ronald Weimer ,  Scott DeBoer ,  Dan Gealy ,  Husam Al-Shareef

发明人： Ronald Weimer ,  Scott DeBoer ,  Dan Gealy ,  Husam Al-Shareef

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/469

CPC分类号： H01L21/3105 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/901

摘要： A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

摘要翻译： 制造半导体器件的方法包括沉积电介质膜并使电介质膜在快速热处理室中进行湿氧化。 该技术可以用于例如在集成电路中形成各种元件，包括栅介质膜以及电容元件。 通过RTP工艺提供的紧密温度控制允许快速进行湿氧化，使得氧化物质不会通过电介质膜显着扩散并扩散到下层。 在电容元件的情况下，该技术还可以有助于降低电介质膜的漏电流，而不会显着降低其电容。

公开(公告)号：US20040046185A1

公开(公告)日：2004-03-11

申请号：US10650070

申请日：2003-08-28

申请人： FUJITSU LIMITED

发明人： Naoya Sashida

IPC分类号： H01L031/0328

CPC分类号： H01L27/11502 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/31612 ,  H01L27/105 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/40 ,  H01L28/55 ,  H01L28/65 ,  Y10S438/901

摘要： There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.

摘要翻译： 提供了一种半导体器件，其包括在硅（半导体）衬底上形成的第一层间绝缘膜（第一绝缘膜），形成在第一层间绝缘膜上并具有下电极，电介质膜和上电极的电容器 形成在所述电容器和所述第一层间绝缘膜上的第四层间绝缘膜（第二绝缘膜）以及形成在所述电容器及其周边上的所述第四层间绝缘膜上的金属图案，以具有与所述第四绝缘膜相反的方向的应力 层间绝缘膜。 结果，可以提高用层间绝缘膜覆盖的电容器的特性。

公开(公告)号：US5016087A

公开(公告)日：1991-05-14

申请号：US480422

申请日：1990-02-15

申请人： Werner O. Haug ,  Erich Klink ,  Karl E. Kroll ,  Thomas Ludwig ,  Helmut Schettler ,  Rainer Stahl ,  Otto M. Wagner

发明人： Werner O. Haug ,  Erich Klink ,  Karl E. Kroll ,  Thomas Ludwig ,  Helmut Schettler ,  Rainer Stahl ,  Otto M. Wagner

IPC分类号： H01L21/60 ,  H01L23/14 ,  H01L23/64

CPC分类号： H01L23/642 ,  H01L23/147 ,  H01L2224/16 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/3011 ,  Y10S257/916 ,  Y10S438/901

摘要： Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented.Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type.The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1).Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship.Said first and second conductive lines are connected to first second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.At least one active integrated circuit chip (1) is mounted and electrically connected to the passive semiconductor interconnection carrier (2).

公开(公告)号：US4536784A

公开(公告)日：1985-08-20

申请号：US541445

申请日：1983-10-13

申请人： Shuzo Nagumo ,  Setsuo Ogura ,  Yukinori Kitamura

发明人： Shuzo Nagumo ,  Setsuo Ogura ,  Yukinori Kitamura

IPC分类号： H01L27/04 ,  H01L21/22 ,  H01L21/331 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/02 ,  H01L27/06 ,  H01L27/08 ,  H01L29/73 ,  H01L29/93 ,  H01L29/92

CPC分类号： H01L21/2205 ,  H01L21/74 ,  H01L27/0244 ,  H01L27/0647 ,  H01L27/0805 ,  H01L29/93 ,  Y10S438/901

摘要： A semiconductor device has a diffused layer of a first conductivity type which extends to a buried layer of a second conductivity type, formed in a manner to extend from a part of a surface of a semiconductor layer of the second conductivity type which is epitaxially grown on a semiconductor substrate of the first conductivity type through the buried layer of the second conductivity type. A semiconductor junction capacitance is formed of the diffused layer of the first conductivity type and the buried layer of the second conductivity type, and the concentration of an impurity to be introduced into the buried layer of the second conductivity type is controlled.

摘要翻译： 半导体器件具有第一导电类型的扩散层，其延伸到第二导电类型的掩埋层，其以从外延生长的第二导电类型的半导体层的表面的一部分延伸的方式形成 通过第二导电类型的掩埋层的第一导电类型的半导体衬底。 半导体结电容由第一导电类型的扩散层和第二导电类型的掩埋层形成，并且控制要引入到第二导电类型的掩埋层中的杂质的浓度。