公开(公告)号：US20070236859A1

公开(公告)日：2007-10-11

申请号：US11401149

申请日：2006-04-10

Applicant: William Borland ,  Thomas Dueber ,  John Summers ,  Olga Renovales ,  Diptarka Majumdar

Inventor： William Borland ,  Thomas Dueber ,  John Summers ,  Olga Renovales ,  Diptarka Majumdar

IPC: H01G2/00 ,  H05K1/16

CPC classification number: H01G2/10 ,  C08G59/621 ,  H01G4/224 ,  H05K1/092 ,  H05K1/162 ,  H05K3/1291 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126

Abstract: An organic encapsulant composition applied to formed-on-foil ceramic capacitors and embedded inside printed wiring boards allows the capacitor to resist printed wiring board chemicals and pass 1000 hours of accelerated life testing conducted under high humidity, elevated temperature and applied DC bias.

Abstract translation: 应用于箔形陶瓷电容器和嵌入式印刷线路板的有机密封剂组合物允许电容器抵抗印刷线路板化学品，并在高湿度，高温和施加的直流偏压下进行1000小时的加速寿命测试。

公开(公告)号：US07253502B2

公开(公告)日：2007-08-07

申请号：US10900385

申请日：2004-07-28

Applicant: Subahu D. Desai ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

Inventor： Subahu D. Desai ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

IPC: H01L23/58

CPC classification number: G11C11/22 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/16 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10159 ,  H01L2224/0401

Abstract: A circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device. The substrate is preferably combined with other dielectric-circuit layered assemblies to form a multilayered substrate on which can be positioned discrete electronic components (e.g., a logic chip) coupled to the internal memory device to work in combination therewith. An electrical assembly capable of using the substrate is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.

Abstract translation: 一种电路化衬底，由至少一层具有导电图案的电介质材料构成。 图案的至少一部分被用作有机存储器件的第一层，该有机存储器件还包括在图案上方的至少第二介电层和相对于下部对准的第二图案，用于实现几个接触点，从而形成 设备。 衬底优选地与其它介电电路分层组件组合以形成多层衬底，在多层衬底上，可以将耦合到内部存储器件的分立电子部件（例如，逻辑芯片）放置在其上以与之组合工作。 还提供了能够使用基板的电气组件，以及适于使用一个或多个这样的电气组件作为其一部分的信息处理系统。

公开(公告)号：US20070146980A1

公开(公告)日：2007-06-28

申请号：US11681457

申请日：2007-03-02

Applicant: Jin-Yong Ahn ,  Chang-Sup Ryu ,  Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun

Inventor： Jin-Yong Ahn ,  Chang-Sup Ryu ,  Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun

IPC: H04R17/00

CPC classification number: H05K1/162 ,  H01G4/1209 ,  H01G4/1218 ,  H01G4/248 ,  H01G4/33 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09881 ,  H05K2203/0568 ,  H05K2203/1366 ,  Y10T29/42

Abstract: Disclosed is a PCB including embedded capacitors and a method of fabricating the same. A dielectric layer is formed using a ceramic material having a high capacitance, thereby assuring that the capacitors each have a high dielectric constant corresponding to the capacitance of a decoupling chip capacitor.

Abstract translation: 公开了一种包括嵌入式电容器的PCB及其制造方法。 使用具有高电容的陶瓷材料形成电介质层，从而确保电容器各自具有对应于去耦芯片电容器的电容的高介电常数。

公开(公告)号：US20070090546A1

公开(公告)日：2007-04-26

申请号：US11338857

申请日：2006-01-25

Applicant: Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John Baniecki ,  Kazuaki Kurihara

Inventor： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John Baniecki ,  Kazuaki Kurihara

IPC: H01L23/29

CPC classification number: H01L23/50 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0733 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599

Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.

Abstract translation: 插入件包括由多个树脂层68,20,32,48形成的基座8; 掩埋在所述多个树脂层的第一树脂层68和所述多个树脂层的第二树脂层20之间的薄膜电容器18a，18b，其包括第一电容器电极12a，12b，第二电容器电极16 与第一电容器电极12a，12b和第二电容器电极16相对，以及形成在第一电容器电极12a，12b和第二电容器电极16之间的相对介电常数为200或更大的电容器电介质膜14 ; 通过基座8形成并电连接到第一电容器电极12a，12b的第一贯通电极77a; 以及通过基底8形成并电连接到第二电容器电极16的第二贯通电极77b。

公开(公告)号：US07183891B2

公开(公告)日：2007-02-27

申请号：US10958442

申请日：2004-10-05

Applicant: Edwin James Harris ,  Tushar Vyas ,  Timothy Pachla ,  James A. Colby

Inventor： Edwin James Harris ,  Tushar Vyas ,  Timothy Pachla ,  James A. Colby

IPC: H01C7/10

CPC classification number: H01C7/12 ,  H01G2/14 ,  H02H9/044 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/167 ,  H05K3/28 ,  H05K2201/0738 ,  H05K2201/09763

Abstract: A voltage variable material (“VVM”) including an insulative binder that is formulated to intrinsically adhere to conductive and non-conductive surfaces is provided. The binder and thus the VVM is self-curable and applicable in a spreadable form that dries before use. The binder eliminates the need to place the VVM in a separate device or to provide separate printed circuit board pads on which to electrically connect the VVM. The binder and thus the VVM can be directly applied to many different types of substrates, such as a rigid FR-4 laminate, a polyimide, a polymer or a multilayer PCB via a process such as screen or stencil printing. In one embodiment, the VVM includes two types of conductive particles, one with a core and one without a core. The VVM can also have core-shell type semiconductive particles.

Abstract translation: 提供了包括被配制为固有地粘附到导电和非导电表面的绝缘粘合剂的电压可变材料（“VVM”）。 粘合剂，因此VVM是可自我修复的，并且可以在使用前干燥的可涂抹形式使用。 粘合剂消除了将VVM放置在单独的装置中的需要，或者提供用于电连接VVM的单独的印刷电路板焊盘。 粘合剂和因此的VVM可以通过诸如筛网或模版印刷的工艺直接应用于许多不同类型的基材，例如刚性FR-4层压板，聚酰亚胺，聚合物或多层PCB。 在一个实施例中，VVM包括两种类型的导电颗粒，一种具有芯和一个不具有芯。 VVM还可以具有核 - 壳型半导体颗粒。

公开(公告)号：US07161241B2

公开(公告)日：2007-01-09

申请号：US10092548

申请日：2002-03-08

Applicant: Junichi Kimura

Inventor： Junichi Kimura

IPC: H01L23/34

CPC classification number: H05K1/16 ,  H01L23/5385 ,  H01L2224/16225 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4605 ,  H05K2201/0154 ,  H05K2201/09763

Abstract: A multi-layer board includes a ceramic layer and plural resin layers which are stacked together. The ceramic layer is provided with an impedance element formed thereon, and the uppermost resin layer is provided with an electronic component mounted thereon. The multi-layer board is stable against a temperature change.

Abstract translation: 多层板包括层叠在一起的陶瓷层和多个树脂层。 陶瓷层上形成有阻抗元件，最上面的树脂层设有安装在其上的电子部件。 多层板对温度变化是稳定的。

公开(公告)号：US20070003781A1

公开(公告)日：2007-01-04

申请号：US11479159

申请日：2006-06-30

Applicant: L. de Rochemont

Inventor： L. de Rochemont

IPC: B32B15/00

CPC classification number: H01Q9/0414 ,  B82Y30/00 ,  C04B2235/768 ,  C04B2235/781 ,  H01C7/003 ,  H01C17/003 ,  H01C17/06533 ,  H01G4/10 ,  H01G4/1209 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/647 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01025 ,  H01L2924/01037 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q15/0086 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/207 ,  H05K2201/017 ,  H05K2201/0175 ,  H05K2201/09763 ,  H05K2203/016 ,  H05K2203/0338 ,  H05K2203/121 ,  Y10T428/12493

Abstract: An electrical component provides a ceramic element located on or in a dielectric substrate between and in contact with a pair of electrical conductors, wherein the ceramic element includes one or more metal oxides having fluctuations in metal-oxide compositional uniformity less than or equal to 1.5 mol % throughout the ceramic element. A method of fabricating an electrical component, provides or forming a ceramic element between and in contact with a pair of electrical conductors on a substrate including depositing a mixture of metalorganic precursors and causing simultaneous decomposition of the metal oxide precursors to form the ceramic element including one or more metal oxides.

Abstract translation: 电气部件提供位于电介质基板上或介质基板之间的陶瓷元件，其与一对电导体接触并接触，其中陶瓷元件包括一种或多种具有小于或等于1.5摩尔的金属 - 氧化物组成均匀性波动的金属氧化物 ％整个陶瓷元件。 一种制造电气部件的方法，在衬底上提供或形成与一对电导体接触的陶瓷元件，包括沉积金属有机前体的混合物并引起金属氧化物前体的同时分解以形成陶瓷元件，包括一个 或更多的金属氧化物。

公开(公告)号：US20060258082A1

公开(公告)日：2006-11-16

申请号：US11459341

申请日：2006-07-22

Applicant: Wei-Chun Yang ,  Chien-Wei Chang

Inventor： Wei-Chun Yang ,  Chien-Wei Chang

IPC: H01L21/8244

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K2201/09763

Abstract: A new structure is provided to replace the existing common planar capacitor structure used in printed circuit boards. The common planar capacitor structure utilizes a single dielectric layer and embedded capacitors with different capacitances achieved by adjusting the sizes of the embedded capacitors' conductive terminals. Since general applications usually require capacitors whose capacitance range covers several orders of magnitude, these embedded capacitors have significant differences in terms of their conductive terminals' sizes. This will make the manufacturing process more complicated and difficult. The new structure combines inorganic material having a specific dielectric constant and polymer having another specific dielectric constant into a singulated coplanar capacitor structure.

Abstract translation: 提供了一种新的结构来代替印刷电路板中现有的普通平面电容器结构。 共同的平面电容器结构利用单个电介质层和通过调整嵌入式电容器的导电端子的尺寸而实现的具有不同电容的嵌入式电容器。 由于一般应用通常需要电容范围为几个数量级的电容器，所以这些嵌入式电容器在其导电端子尺寸方面存在显着差异。 这将使制造过程更加复杂和困难。 新结构将具有特定介电常数的无机材料和具有另一特定介电常数的聚合物结合成单个共面电容器结构。

公开(公告)号：US20060215380A1

公开(公告)日：2006-09-28

申请号：US11089450

申请日：2005-03-24

Applicant: Chee Lu ,  Boon Lok ,  Kai Chua ,  Lai Wai

Inventor： Chee Lu ,  Boon Lok ,  Kai Chua ,  Lai Wai

IPC: H05K1/18

CPC classification number: H01G4/232 ,  H01G4/40 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/185 ,  H05K3/429 ,  H05K2201/09718 ,  H05K2201/09763 ,  H01L2224/0401

Abstract: An embedded capacitor structure comprising a main body; at least one embedded capacitor, having a first electrode, a dielectric layer, and a second electrode, formed in the main body; and at least one via electrical connection formed in the main body; wherein at least one of the first and second electrodes is free from direct electrical connection to the via electrical connections.

公开(公告)号：US07100276B2

公开(公告)日：2006-09-05

申请号：US11023499

申请日：2004-12-29

Applicant: Yoshitaka Fukuoka ,  Tooru Serizawa ,  Hiroshi Yagi ,  Osamu Shimada ,  Hiroyuki Hirai ,  Yuji Yamaguchi

Inventor： Yoshitaka Fukuoka ,  Tooru Serizawa ,  Hiroshi Yagi ,  Osamu Shimada ,  Hiroyuki Hirai ,  Yuji Yamaguchi

IPC: H05K3/36

CPC classification number: H05K1/162 ,  H05K1/095 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09763 ,  H05K2203/0338 ,  H05K2203/1189 ,  Y10T29/4902 ,  Y10T29/49099 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A fabricating method of a wiring board provided with passive elements is disclosed. The fabricating method includes coating one or both of resistive paste and dielectric paste on at least any one of first surfaces of a first metal foil and a second metal foil each of which has a first surface and a second surface; arranging an insulating board having thermo-plasticity and thermo-setting properties so as to face the first surface of the first metal foil, and arranging the first surface side of the second metal foil so as to face a surface different from a surface to which the first metal foil faces of the insulating board; forming a double-sided wiring board by stacking, pressurizing and heating the arranged first metal foil, insulating board, and second metal foil, and thereby integrating these; and patterning the first metal foil and/or the second metal foil.

Abstract translation: 公开了一种具有无源元件的布线板的制造方法。 制造方法包括在第一金属箔和第二金属箔的至少一个第一表面上涂覆电阻浆料和电介质浆料中的一种或两种，每个第一表面具有第一表面和第二表面; 布置具有热塑性和热固性的绝缘板，以便面对第一金属箔的第一表面，并且将第二金属箔的第一表面侧布置成面对不同于表面的表面 绝缘板的第一金属箔面; 通过对所配置的第一金属箔，绝缘板和第二金属箔进行堆叠，加压和加热来形成双面布线板，从而将它们集成; 以及图案化第一金属箔和/或第二金属箔。