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公开(公告)号：US20160315621A1
公开(公告)日：2016-10-27
申请号：US14691738
申请日：2015-04-21
Applicant: STMicroelectronics International N.V.
Inventor： Jeet Narayan Tiwari , Nitin Gupta
IPC: H03K21/02
CPC classification number: H03K21/026 , H03K21/00 , H03K23/00 , H03K23/58 , H03K23/667 , H03K23/68
Abstract: A method of dividing a clock signal by an input signal of N bits with M most significant bits is described herein. The method includes dividing the clock signal by the most significant bits of the input signal 2N-M−1 times out of 2N-M divisions of the clock signal, using a divider. The clock signal is divided by a sum of the most significant bits and the least significant bits one time out of 2N-M divisions of the clock signal, using the divider. The clock signal is also divided by 2N-M, 2N-M times, using the divider.
Abstract translation: 本文描述了将时钟信号除以具有M个最高有效位的N位的输入信号的方法。 该方法包括使用分频器将时钟信号除以时钟信号的2N-M分频之外的输入信号2N-M-1的最高有效位。 使用分频器，将时钟信号除以时钟信号的2N-M分频之外的最高有效位和最低有效位之和。 使用分频器也可以将时钟信号除以2N-M，2N-M次。
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公开(公告)号：US20160308431A1
公开(公告)日：2016-10-20
申请号：US14957752
申请日：2015-12-03
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Patrik ARNO , Eric CIROT
CPC classification number: H05K3/32 , H02M1/08 , H02M3/1588 , H02M7/483 , H02M2001/0054 , H02M2007/4835 , H03K17/162 , Y02B70/1466 , Y02B70/1491
Abstract: A circuit is for controlling a power transistor of a DC/DC converter. The circuit may include first and second first transistors coupled in series between a first reference voltage and a control terminal of the power transistor, the first and second transistors defining a first junction node. The circuit may include third and fourth transistors coupled in series between the control terminal and a second reference voltage, the third and fourth transistors defining a second junction node. The first and second transistors may have a first conductivity type different from a second conductivity type of the third and fourth transistors. The circuit may include a capacitive element coupled between the first and second junction nodes.
Abstract translation: 电路用于控制DC / DC转换器的功率晶体管。 电路可以包括串联耦合在第一参考电压和功率晶体管的控制端之间的第一和第二晶体管，第一和第二晶体管限定第一结节点。 电路可以包括串联耦合在控制端和第二参考电压之间的第三和第四晶体管，第三和第四晶体管限定第二连接节点。 第一和第二晶体管可以具有不同于第三和第四晶体管的第二导电类型的第一导电类型。 电路可以包括耦合在第一和第二连接节点之间的电容元件。
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公开(公告)号：US09466347B1
公开(公告)日：2016-10-11
申请号：US14971403
申请日：2015-12-16
Inventor： Marco Pasotti , Vikas Rana
CPC classification number: G11C8/10 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C13/0069
Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, a plurality of wordlines coupled to the array of PCM cells, and a row decoder circuit coupled to the plurality of wordlines. The row decoder circuit includes a first low voltage logic gate and a first high voltage level shifter coupled to the first low voltage logic gate. The row decoder circuit also includes a second low voltage logic gate, a second high voltage level shifter coupled to the second low voltage logic gate, and a first low voltage logic circuit coupled to the second low voltage logic gate. In addition, the row decoder circuit includes a second low voltage logic circuit coupled to the second low voltage logic gate, and a low voltage wordline driver having an input coupled to the outputs of the first and second low voltage logic gates, and an output coupled to a selected wordline.
Abstract translation: 集成电路包括相变存储器（PCM）单元的阵列，耦合到PCM单元阵列的多个字线以及耦合到多个字线的行解码器电路。 行解码器电路包括耦合到第一低电压逻辑门的第一低电压逻辑门和第一高电压电平移位器。 行解码器电路还包括第二低电压逻辑门，耦合到第二低电压逻辑门的第二高电压电平移位器和耦合到第二低电压逻辑门的第一低电压逻辑电路。 此外，行解码器电路包括耦合到第二低电压逻辑门的第二低电压逻辑电路和具有耦合到第一和第二低电压逻辑门的输出的输入的低电压字线驱动器，以及耦合到 到一个选定的字线。
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公开(公告)号：US09438254B1
公开(公告)日：2016-09-06
申请号：US14718597
申请日：2015-05-21
Applicant: STMicroelectronics International N.V.
Inventor： Abhirup Lahiri
CPC classification number: H03L7/0891 , H03L7/099
Abstract: A phase-locked-loop includes a phase-frequency-detector (PFD) comparing phases of an input signal and feedback signal, and generating therefrom control signals. An attenuation circuit in series with the PFD includes a filter between a voltage-controlled-oscillator (VCO) control node and ground. A buffer is coupled to the VCO control node. An impedance network is coupled to the VCO control node and has an impedance element coupled to a first current source so voltage at the VCO control node increases when control signals indicate the phase of the input signal leads the feedback signal, and coupled to a second current source so voltage at the VCO control node decreases when control signals indicate a lagging phase. A VCO is coupled to the VCO control node to generate an output signal, with the phase of the output signal matching the input signal. The feedback signal is based upon the output signal.
Abstract translation: 锁相环包括比较输入信号和反馈信号的相位的相位频率检测器（PFD），并从其产生控制信号。 与PFD串联的衰减电路包括压控振荡器（VCO）控制节点和地之间的滤波器。 缓冲器耦合到VCO控制节点。 阻抗网络耦合到VCO控制节点并且具有耦合到第一电流源的阻抗元件，因此当控制信号指示输入信号的相位引导反馈信号并耦合到第二电流时，VCO控制节点处的电压增加 当控制信号指示滞后相位时，VCO控制节点处的源极电压降低。 VCO耦合到VCO控制节点以产生输出信号，输出信号的相位与输入信号匹配。 反馈信号基于输出信号。
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公开(公告)号：US09436610B2
公开(公告)日：2016-09-06
申请号：US14464750
申请日：2014-08-21
Applicant: STMicroelectronics International N.V.
Inventor： Gilles Ries , Ennio Salemi , Sana Ben Alaya
CPC classification number: G06F12/0862 , G06F12/1027 , G06F12/1063 , G06F2212/304 , G06F2212/507 , G06F2212/602 , G06F2212/684
Abstract: A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit.
Abstract translation: 存储器管理单元可以将页面表移动请求发送到主存储器系统中的页表描述符并且接收地址转换信息，其中页表步行请求包括指定进一步的地址转换信息的量的信息，并且接收另外的地址转换 信息。 高速缓存单元可以拦截页表行走请求，并且修改被拦截的页表行走请求的内容，使得指定进一步的地址转换信息量的信息从第一数量扩展到大于第一数量的第二数量。 高速缓存单元可以存储第二数量的进一步的地址转换信息，以便与当前数据请求之后的数据请求一起使用，并且基于与已经存储在地址转换信息中的地址转换信息相关联的被拦截的页表移动请求来提供地址转换信息 缓存单元。
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Patent Agency Ranking
公开(公告)号：US09407224B2
公开(公告)日：2016-08-02
申请号：US14311086
申请日：2014-06-20
Applicant: STMicroelectronics International N.V.
Inventor： Carlo Pinna , Alessandro Mecchia , Paolo Pesenti
Abstract: The present disclosure refers to a digital microphone device providing a single-bit Pulse Density Modulation PDM output signal. The digital microphone comprises a microphone, arranged to convert an acoustic input signal into an analog electrical signal, and a preamplifier, having a variable gain, arranged to receive the analog electrical signal and to provide an amplified analog electrical signal, depending on the variable gain. The variable gain depends on a gain control signal. The digital microphone further comprises an Analog-to-Digital Converter block, arranged to receive the amplified analog electrical signal and to convert it into a respective digital signal; and a compensation block, arranged to receive the digital signal and to perform a digital operation on such digital signal, on the basis of a compensation signal, to generate a compensated signal. Furthermore, the digital microphone comprises an Automatic Gain Controller block 25, arranged to detect the digital signal and to generate said gain control signal, on the basis of the detected digital signal. The Automatic Gain Controller block is further arranged to generate the compensation signal, on the basis of the control signal, and to provide the compensation signal to the compensation block, to compensate a variation of the digital signal resulting from the variable gain of the preamplifier. Finally, the digital microphone device comprises a conversion block, arranged to receive the compensated signal and to convert it into the single-bit PDM output signal.
Abstract translation: 本公开涉及提供单位脉冲密度调制PDM输出信号的数字麦克风装置。 数字麦克风包括麦克风，其布置成将声输入信号转换为模拟电信号，以及具有可变增益的前置放大器，其布置成接收模拟电信号并根据可变增益提供放大的模拟电信号 。 可变增益取决于增益控制信号。 数字麦克风还包括模数转换器模块，被布置为接收放大的模拟电信号并将其转换成相应的数字信号; 以及补偿块，被布置成基于补偿信号接收数字信号并对这种数字信号执行数字操作，以产生补偿信号。 此外，数字麦克风包括自动增益控制器块25，其被布置为基于检测到的数字信号来检测数字信号并产生所述增益控制信号。 自动增益控制器块还被布置成基于控制信号产生补偿信号，并且向补偿块提供补偿信号，以补偿由前置放大器的可变增益引起的数字信号的变化。 最后，数字麦克风装置包括转换块，被布置成接收经补偿的信号并将其转换成单位PDM输出信号。
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公开(公告)号：US09379728B1
公开(公告)日：2016-06-28
申请号：US14751456
申请日：2015-06-26
Applicant: STMicroelectronics International N.V.
Inventor： Pratap Narayan Singh , Shiva Sharath Babu Kaleru , Ankur Bal , Mohit Singh , Rakesh Malik
CPC classification number: H03M1/1023 , H03M1/1047 , H03M1/66
Abstract: A digital-to-analog converter has an output. An analog-to-digital converter senses a voltage at the output of the digital-to-analog converter and generates a digital voltage signal. A source mismatch estimator processes the digital voltage signal to output an error signal indicative of current source mismatch within the digital-to-analog converter. An error code generator generates a digital calibration signal from the error signal. The digital calibration signal is converted by a redundancy digital-to-analog converter to an analog compensation signal for application to the output of analog-to-digital converter to nullify effects of the current source mismatch.
Abstract translation: 一个数模转换器有一个输出。 模拟 - 数字转换器感测数模转换器输出端的电压，并产生一个数字电压信号。 源不匹配估计器处理数字电压信号以输出指示数模转换器内的电流源失配的误差信号。 错误代码发生器从误差信号产生数字校准信号。 数字校准信号由冗余数模转换器转换为模拟补偿信号，以应用于模数转换器的输出，以消除电流源不匹配的影响。
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338.发明授权Oversampling CDR which compensates frequency difference without elasticity buffer 有权过采样CDR，补偿频率差，无弹性缓冲公开(公告)号：US09356770B2
公开(公告)日：2016-05-31
申请号：US14231499
申请日：2014-03-31
Applicant: STMicroelectronics International N.V.
Inventor： Abhishek Chowdhary , Vivek Uppal , Alok Kaushik , Sajal Kumar Mandal , Tapas Nandy , Sanjeev Chopra
CPC classification number: H04L7/0087 , H03L7/0807 , H03L7/091 , H04L7/0004 , H04L7/005 , H04L7/033 , H04L7/0331 , H04L7/0338 , H04L25/03057 , H04L43/022
Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.
Abstract translation: 补偿过采样CDR中的频率差的方法，算法，架构，电路和/或系统。 过采样的CDR使用可编程分频器，其分频比从其通常的分频比改变一个或多个周期，当任一方向上的累积相位移动超过阈值时。 因此，过采样CDR中的弹性缓冲器可以被制造得更小或完全消除，导致较少的面积，并且减少或消除了最大允许突发尺寸对ppm差的依赖性。 门限可以保持可编程，并且超过一半单位间隔，以提供对高频抖动的鲁棒性。
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公开(公告)号：US20160149491A1
公开(公告)日：2016-05-26
申请号：US14549458
申请日：2014-11-20
Applicant: STMicroelectronics International N.V.
Inventor： Phalguni Bala , Hiten Advani
IPC: H02M3/158
CPC classification number: H02M3/06 , H02M2001/0022
Abstract: According to an embodiment, a circuit includes a protection voltage generator coupled to a first voltage node, a second voltage node, and a ground voltage node, the protection voltage generator configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node, and a voltage protection ladder coupled between the first voltage node and a low voltage circuit, the voltage protection ladder coupled to the plurality of protection voltages at the first plurality of nodes, the voltage protection ladder configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.
Abstract translation: 根据实施例，电路包括耦合到第一电压节点，第二电压节点和接地电压节点的保护电压发生器，所述保护电压发生器被配置为在基于第一多个节点的基础上产生多个保护电压 所述第一电压节点和所述第二电压节点以及耦合在所述第一电压节点和低电压电路之间的电压保护梯，所述电压保护梯级耦合到所述第一多个节点处的所述多个保护电压，所述电压保护梯配置 以产生基于第一电压节点和多个保护电压的第一低电压。
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340.发明授权公开(公告)号：US09342085B2
公开(公告)日：2016-05-17
申请号：US14512564
申请日：2014-10-13
Applicant: STMicroelectronics International N.V.
Inventor： Hemant Shukla , Saurabh Kumar Singh , Nitin Bansal
Abstract: An electronic device includes a power supply, a ground, and an intermediate ground having a voltage less than a voltage of the power supply and greater than a voltage of the ground. The electronic device also includes an error amplifier having an input stage coupled between the power supply and the ground, and an output stage coupled between the power supply and the intermediate ground. A ballast transistor is coupled to receive an output from the error amplifier. A feedback circuit is coupled to an output of the ballast transistor to generate feedback signals, and the error amplifier operates in response to the feedback signals.
Abstract translation: 电子设备包括电源，接地和具有小于电源电压的电压并且大于地的电压的中间接地。 电子设备还包括误差放大器，其具有耦合在电源和地之间的输入级，以及耦合在电源和中间接地之间的输出级。 耦合镇流器晶体管以接收来自误差放大器的输出。 反馈电路耦合到镇流器晶体管的输出以产生反馈信号，误差放大器响应于反馈信号而工作。
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