公开(公告)号：US10164104B2

公开(公告)日：2018-12-25

申请号：US15343590

申请日：2016-11-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51

Abstract: A device includes an air-gap (i.e., air-gap spacer) formed in situ during the selective, non-conformal deposition of a conductive material. The air-gap is disposed between source/drain contacts and a gate conductor of the device and beneath a portion of the conductive material, and is configured to decrease capacitive coupling between adjacent conductive elements. Prior to deposition of the conductive material, source/drain contact structures are recessed and a selective etch is used to remove sidewall spacers that are disposed between the source/drain contacts and the gate structures.

公开(公告)号：US10164041B1

公开(公告)日：2018-12-25

申请号：US15790216

申请日：2017-10-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Julien Frougier ,  Hui Zang ,  Min-hwa Chi

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786 ,  H01L27/088

Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

公开(公告)号：US10157796B1

公开(公告)日：2018-12-18

申请号：US15811953

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Chanro Park ,  Ruilong Xie ,  Pei Liu

IPC: H01L21/8234 ,  H01L31/05 ,  H01L21/311 ,  H01L23/544 ,  H01L21/027 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/02

Abstract: The disclosure relates to methods including: forming a soft mask; forming a first marking trench within a portion of the soft mask by selectively removing a portion of the soft mask at a first location, over one of a pair of gate trenches; forming an insulative liner on the soft mask and within the first marking trench; forming an anti-reflective film on the insulative liner and within the first marking trench; selectively removing the anti-reflective film and the insulative liner at a second location to expose a portion of the soft mask positioned over the other one of the pair of gate trenches; forming a second marking trench by removing another portion of the soft mask at the second location; and removing a portion of the soft mask at the first and second marking trenches to expose a lower surface of each of the pair of gate trenches.

公开(公告)号：US10121702B1

公开(公告)日：2018-11-06

申请号：US15638087

申请日：2017-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Min Gyu Sung ,  Ruilong Xie ,  Puneet H. Suvarna

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535

Abstract: At least one method, apparatus and system disclosed herein involves performing an early-process of source/drain (S/D) contact cut and S/D contact etch steps for manufacturing a finFET device. A gate structure, a source structure, and a drain structure of a transistor are formed. The gate structure comprises a dummy gate region, a gate spacer, and a liner. A source/drain (S/D) contact cut process is performed. An S/D contact etch process is performed. A replacement metal gate (RMG) process is performed subsequent to performing the S/D contact etch process. An S/D contact metallization process is performed.

公开(公告)号：US20180308930A1

公开(公告)日：2018-10-25

申请号：US15992431

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A vertical transistor device includes a vertically-oriented channel semiconductor (VOCS) structure positioned above a substrate and a first bottom spacer positioned above the substrate adjacent the VOCS structure. The first bottom spacer extends around less than an entirety of a perimeter of the VOCS structure. A gate structure is positioned around the VOCS structure. Only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure. The air gap extends around a majority of a perimeter of the VOCS structure and a second bottom spacer positioned above the substrate. An upper portion of the second bottom spacer contacts a material formed around the VOCS structure so as to seal the air gap. The second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap.

公开(公告)号：US10096674B2

公开(公告)日：2018-10-09

申请号：US15717336

申请日：2017-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

公开(公告)号：US10084068B2

公开(公告)日：2018-09-25

申请号：US15631385

申请日：2017-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/22 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L29/66795 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/22 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US10084053B1

公开(公告)日：2018-09-25

申请号：US15470205

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/82 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/417

Abstract: Structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor. A first metal gate electrode and a second metal gate electrode are formed that are embedded in a first dielectric layer. A second dielectric layer is formed on the first metal gate electrode, the second metal gate electrode, and the first dielectric layer. An opening is formed in the second dielectric layer that extends in a vertical direction to expose a section of the first metal gate electrode. The section of the first metal gate electrode is removed, while the second metal gate electrode is masked by the second dielectric layer, to define a gate cut at a location of the opening. The gate cut may be subsequently filled by dielectric material.

公开(公告)号：US10068804B2

公开(公告)日：2018-09-04

申请号：US15423326

申请日：2017-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Peng Xu ,  Chun Wing Yeung

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L21/321 ,  H01L29/08 ,  H01L29/417 ,  H01L21/66

CPC classification number: H01L21/823431 ,  H01L21/823425 ,  H01L22/12 ,  H01L22/20 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method and system are disclosed herein for an adjustable effective fin height in a gate region of a finFET device. Fin structures, each having a first height, a fin, an oxide liner, and a nitride liner, are formed. A first portion of the nitride liner is removed. A first portion of the oxide liner is removed. A second portion of the nitride liner in a gate portion of the finFET. Source/drain(s) are formed, and a nitride spacer between the source/drain and the gate portion is formed. A second portion of the oxide liner is exposed by removing the second portion of the nitride liner, exposing a second portion of the fin, wherein the first and second exposed portions of the fin being an effective fin height in the gate portion.

公开(公告)号：US10050118B2

公开(公告)日：2018-08-14

申请号：US14269566

申请日：2014-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ryan Ryoung-han Kim ,  Chanro Park ,  William James Taylor, Jr. ,  John A. Iacoponi

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/06 ,  H01L29/78

Abstract: In one aspect a semiconductor device as set forth herein can include a spacer having a first section of a first material and a second section of a second material, the second section disposed above a certain elevation and the first section disposed below the certain elevation. In one aspect a semiconductor device as set forth herein can include a conductive gate structure having a first length at elevations below a certain elevation and a second length at elevations above the certain elevation, the second length being less than the first length. A semiconductor device having one or more of a plural material spacer or a reduced length upper elevation conductive gate structure can feature a reduced likelihood of electrical shorting.