公开(公告)号：US20180196462A1

公开(公告)日：2018-07-12

申请号：US15863703

申请日：2018-01-05

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F1/08 ,  G11C7/22 ,  G11C7/10 ,  G11C7/04 ,  G06F1/04 ,  G11C7/02 ,  G06F1/10 ,  G06F1/06 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12 ,  G11C7/02 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

公开(公告)号：US20180157615A1

公开(公告)日：2018-06-07

申请号：US15813963

申请日：2017-11-15

Applicant: Rambus Inc.

Inventor： Mark A. Horowitz ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC: G06F13/42 ,  G06F3/06

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

公开(公告)号：US20180152327A1

公开(公告)日：2018-05-31

申请号：US15827777

申请日：2017-11-30

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC: H04L25/03 ,  H04B1/12

CPC classification number: H04L25/03159 ,  H04B1/123 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03636

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

公开(公告)号：US20180150420A1

公开(公告)日：2018-05-31

申请号：US15827825

申请日：2017-11-30

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ian Shaeffer

IPC: G06F13/16 ,  G11C11/4093 ,  G11C11/409 ,  G11C11/4076 ,  G06F3/06

CPC classification number: G06F13/1689 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0683 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  Y02D10/14

Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

公开(公告)号：US09985806B2

公开(公告)日：2018-05-29

申请号：US15402981

申请日：2017-01-10

Applicant: Rambus Inc.

Inventor： Ramin Farjad-Rad

IPC: H04L25/03 ,  H04L25/08

CPC classification number: H04L25/03159 ,  H04L25/03019 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/085 ,  H04L2025/03681

Abstract: An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

公开(公告)号：US09983830B2

公开(公告)日：2018-05-29

申请号：US15022176

申请日：2014-09-23

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G11C7/10 ,  G11C29/02 ,  G06F11/10 ,  G11C29/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0673 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2207/107

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

公开(公告)号：US20180145670A1

公开(公告)日：2018-05-24

申请号：US15824892

申请日：2017-11-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian S. Leibowitz ,  Jared Zerbe

IPC: H03K5/13 ,  G11C29/02 ,  G11C7/22 ,  G11C7/10 ,  G06F13/16 ,  G11C7/04 ,  G06F13/42 ,  G06F13/00

Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

公开(公告)号：US20180137067A1

公开(公告)日：2018-05-17

申请号：US15808595

申请日：2017-11-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/16 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US09965008B2

公开(公告)日：2018-05-08

申请号：US14835568

申请日：2015-08-25

Applicant: Rambus Inc.

Inventor： Stephen G. Tell

IPC: G06F12/02 ,  G06F1/26 ,  G06F1/10 ,  G06F13/40 ,  H04L7/02 ,  G06F13/38 ,  G11C7/10 ,  H03K19/177

CPC classification number: G06F1/26 ,  G06F1/10 ,  G06F12/0246 ,  G06F13/382 ,  G06F13/4072 ,  G06F2212/7201 ,  G11C7/1072 ,  H03K19/1776 ,  H04L7/02

Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.

公开(公告)号：US20180102923A1

公开(公告)日：2018-04-12

申请号：US15715032

申请日：2017-09-25

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Vladimir M. Stojanovic ,  Fred F. Chen

IPC: H04L25/03 ,  H04B1/10 ,  H04L7/033 ,  H04L7/00

CPC classification number: H04L25/03019 ,  H04B1/1081 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/03025 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885

Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.