公开(公告)号：US07879653B2

公开(公告)日：2011-02-01

申请号：US12189165

申请日：2008-08-10

申请人： Hung-Tsun Lin

发明人： Hung-Tsun Lin

IPC分类号： H01L21/60

CPC分类号： H01L21/561 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/10165 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to the leads. The encapsulant encapsulates the chip and the leads and has a plurality of cavities reaching to the outer pads to form an electroplated layer on the outer pads and embedded in the cavities. Accordingly, under the advantages of lower cost and higher thermal dissipation, the conventional substrates and their solder masks for BGA (Ball Grid Array) or LGA (Land Grid Array) packages can be replaced. The leads encapsulated in the encapsulant have a better bonding strength and the electroplated layer embedded in the encapsulant will not be damaged during shipping, handling, or storing the semiconductor packages. Furthermore, the manufacturing processes include two half-etching steps to form the half-etched leadframe where a second half-etching step is performed after forming the encapsulant and before forming the electroplated layer.

摘要翻译： 公开了一种具有嵌入密封剂中的电镀层的无引线半导体封装及其制造工艺。 封装主要包括半蚀刻引线框架，芯片，密封剂和电镀层。 半蚀刻引线框架具有多个引线和与引线整体连接的多个外焊盘。 密封剂封装芯片和引线，并且具有到达外部焊盘的多个空腔，以在外部焊盘上形成电镀层并嵌入空腔中。 因此，在降低成本和较高散热的优点下，可以更换常规基板及其用于BGA（球栅阵列）或LGA（Land Grid Array）封装的焊接掩模。 封装在密封剂中的引线具有更好的接合强度，并且嵌入密封剂中的电镀层在运输，处理或存储半导体封装期间不会被损坏。 此外，制造工艺包括形成半蚀刻引线框架的两个半蚀刻步骤，其中在形成密封剂之后和形成电镀层之前执行第二半蚀刻步骤。

公开(公告)号：US07847414B2

公开(公告)日：2010-12-07

申请号：US12147929

申请日：2008-06-27

申请人： Geng-Shin Shen ,  David Wei Wang

发明人： Geng-Shin Shen ,  David Wei Wang

IPC分类号： H01L23/48 ,  H01L23/538 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer is provided. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the second substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. The first B-staged adhesive layer is adhered on the first substrate. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps.

摘要翻译： 提供了包括第一基板，第二基板，多个凸块，第一B阶粘合剂层和第二B阶粘合剂层的芯片封装结构。 第一基板具有多个第一接合焊盘。 第二基板具有多个第二接合焊盘，第二基板设置在第一基板的上方。 所述凸块设置在所述第一基板和所述第二基板之间，其中所述第一接合焊盘中的每一个分别经由所述凸块之一电连接到所述第二接合焊盘中的一个。 第一B级粘合剂层粘附在第一基底上。 第二B阶粘合剂层粘附在第一B阶粘合剂层和第二基底之间，其中第一B阶粘合剂层和第二B阶粘合剂层包封凸块。

公开(公告)号：US20100264540A1

公开(公告)日：2010-10-21

申请号：US12825811

申请日：2010-06-29

申请人： Hung Tsun Lin ,  Wu Chang Tu ,  Cheng Ting Wu

发明人： Hung Tsun Lin ,  Wu Chang Tu ,  Cheng Ting Wu

IPC分类号： H01L23/49 ,  H05K1/11

CPC分类号： H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/585 ,  H01L24/28 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83138 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed.

摘要翻译： IC封装主要包括基板，管芯安装层，芯片，至少一个接合线和多个电连接部件。 基板具有顶表面和底表面，其中顶表面包括用于设置管芯附接层的管芯附着区域。 芯片通过管芯附着层附接到管芯附着区域，并通过电连接部件与衬底电连接。 接合线的两端接合到基板的顶表面上的两个互连指状物，其中至少一部分接合线被封装在管芯附着层中以替代传统衬底内部的一些布线或通孔。 因此，衬底具有简单且降低的布线层，即降低衬底成本。 也显示了相应IC封装的芯片载体。

公开(公告)号：US07749806B2

公开(公告)日：2010-07-06

申请号：US12169120

申请日：2008-07-08

申请人： Geng-Shin Shen ,  David Wei Wang

发明人： Geng-Shin Shen ,  David Wei Wang

IPC分类号： H01L21/00

CPC分类号： H01L24/90 ,  H01L24/12 ,  H01L24/16 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

摘要翻译： 提供了芯片封装结构的制造工艺。 首先，提供具有多个第一接合焊盘的第一基板和具有多个第二接合焊盘的第二基板，其中在第一基板的第一接合焊盘上形成多个凸点。 在第一基板上形成第一两层粘合剂层，并将其B层状化以形成第一B阶粘合剂层。 在第二基板上形成第二两层粘合剂层，并且被B阶段化以形成第二B阶粘合剂层。 然后，第一基板和第二基板经由第一B阶粘合剂层和第二B阶粘合剂层接合，使得每个第一接合焊盘分别经由第一接合焊盘中的一个电连接到第二接合焊盘中的一个 颠簸

公开(公告)号：US20100151624A1

公开(公告)日：2010-06-17

申请号：US12714646

申请日：2010-03-01

申请人： Geng-Shin Shen ,  David Wei Wang

发明人： Geng-Shin Shen ,  David Wei Wang

IPC分类号： H01L21/50

CPC分类号： H01L24/90 ,  H01L24/12 ,  H01L24/16 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provided, wherein bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first and second B-staged adhesive layer such that the bumps pierce through the second B-staged adhesive layer and are electrically connected to the second bonding pads, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

摘要翻译： 提供了芯片封装结构的制造工艺。 首先，提供具有多个第一接合焊盘的第一基板和具有多个第二接合焊盘的第二基板，其中在第一基板的第一接合焊盘上形成凸块。 在第一基板上形成第一两层粘合剂层，并将其B层状化以形成第一B阶粘合剂层。 在第二基板上形成第二两层粘合剂层，并且被B阶段化以形成第二B阶粘合剂层。 然后，第一基板和第二基板经由第一和第二B阶粘合剂层接合，使得凸块穿过第二B阶粘合剂层并电连接到第二接合焊盘，其中第一接合 焊盘经由凸块之一分别电连接到第二接合焊盘之一。

公开(公告)号：US07696443B2

公开(公告)日：2010-04-13

申请号：US11188860

申请日：2005-07-26

申请人： Yi-Chang Lee ,  An-Hong Liu ,  Yeong-Her Wang ,  Yeong-Ching Chao ,  Yao-Jung Lee

发明人： Yi-Chang Lee ,  An-Hong Liu ,  Yeong-Her Wang ,  Yeong-Ching Chao ,  Yao-Jung Lee

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H01L24/72 ,  G01R1/06727 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3025 ,  H01L2924/351 ,  H01R13/2407 ,  H05K1/0216 ,  H05K3/4092 ,  H01L2924/00

摘要： An electronic device comprises a substrate and at least a warped spring connector. The substrate has a signal bonding pad and a ground plane. The warped spring connector is disposed on the substrate and is connected to the bonding pad. The warped spring connector includes at least a ground lead electrically connected to the ground plane, a dielectric layer on the ground lead, and a transmitting lead on the dielectric layer. The transmitting lead is bonded to the bonding pad. The ground lead is isolated from and close to the transmitting lead to solve cross-talk and noise problem. Furthermore, the coefficient of thermal expansion of the transmitting lead is different from that of the dielectric layer or the ground lead such that the warped spring connector has a suspending end suspending away from the substrate.

摘要翻译： 电子设备包括基板和至少一个翘曲的弹簧连接器。 衬底具有信号焊盘和接地层。 翘曲弹簧连接器设置在基板上并连接到接合垫。 翘曲弹簧连接器至少包括电连接到接地平面的接地引线，接地引线上的电介质层和介电层上的传输引线。 传输引线接合到焊盘。 接地线与发射线隔离并靠近发射线，以解决串扰和噪声问题。 此外，传输引线的热膨胀系数与电介质层或接地引线的热膨胀系数不同，使得翘曲弹簧连接器具有悬挂远离基板的悬挂端。

公开(公告)号：US07656020B2

公开(公告)日：2010-02-02

申请号：US11822113

申请日：2007-07-02

申请人： Cheng Tang Huang

发明人： Cheng Tang Huang

IPC分类号： H01L23/488 ,  H01L23/495

CPC分类号： H01L24/11 ,  H01L23/525 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

摘要： A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving space. The lifting layer and conductive layer are formed in the receiving space, wherein the conductive layer extends for connection to a bump. The lifting layer is partially connected to the dielectric layer. As a result, the conductive layer can be stably deposited on the edge of the dielectric layer for enhancing the reliability of the packaging conductive structure.

摘要翻译： 提供了一种用于半导体衬底的封装导电结构以及用于形成该结构的方法。 包装导电结构的电介质层部分覆盖半导体衬底的金属层并具有接收空间。 提升层和导电层形成在接收空间中，其中导电层延伸以连接到凸块。 提升层部分连接到电介质层。 结果，导电层可以稳定地沉积在电介质层的边缘上，以提高封装导电结构的可靠性。

公开(公告)号：US07651886B2

公开(公告)日：2010-01-26

申请号：US11451997

申请日：2006-06-12

申请人： Jiun-Heng Wang

发明人： Jiun-Heng Wang

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05073 ,  H01L2224/05558 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2924/0001 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor device including a circuit structure and a protective layer is provided. The circuit structure has multiple contacts. The protective layer is located on the circuit structure and has multiple openings and multiple protrusions, wherein the contacts are exposed by the openings and the protrusions are located on the contacts.

摘要翻译： 提供了包括电路结构和保护层的半导体器件。 电路结构有多个触点。 保护层位于电路结构上，具有多个开口和多个突起，其中触点由开口露出，并且突起位于触点上。

公开(公告)号：US07642137B2

公开(公告)日：2010-01-05

申请号：US11746654

申请日：2007-05-10

申请人： Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

发明人： Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

IPC分类号： H01L21/44

CPC分类号： H01L21/563 ,  H01L23/3135 ,  H01L24/97 ,  H01L33/642 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

摘要： A chip package including a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer is provided. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.

摘要翻译： 包括热增强板的芯片封装，在热增强板周围接触并与热增强板电绝缘，设置在触点和热增强板上的膜状电路层，导电粘合剂层，第一模制件和 提供设置在膜状电路层上的至少一个芯片。 导电性粘合剂层设置在触点和通过导电粘合剂层与触点电连接的膜状电路层之间。 芯片具有背面，有源表面和设置在其上的许多凸块，并且芯片经由凸块电连接到膜状电路层。 第一模制品至少封装热增强板的一部分，导电粘合剂层，触点的一部分和膜状电路层的至少一部分。 因此，提高了发光芯片封装的散热效率。

公开(公告)号：US07579676B2

公开(公告)日：2009-08-25

申请号：US11580310

申请日：2006-10-13

申请人： Hung-Tsun Lin

发明人： Hung-Tsun Lin

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L21/4828 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49541 ,  H01L24/48 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A leadless leadframe has a plurality of bottom leads and a plurality of top soldering pads formed in different layers. After encapsulation and before solder ball placement, a half-etching process is performed to remove the bottom leads to make the top soldering pads electrically isolated, exposed and embedded in the encapsulant for solder ball placement where the soldering area of the top soldering pads is defined without the need of solder mask(s) to solve the diffusion of solder balls on the leads during reflow.

摘要翻译： 无引线框架具有多个底部引线和形成在不同层中的多个顶部焊盘。 在封装之后和焊球放置之前，进行半蚀刻工艺以去除底部引线，使顶部焊盘电隔离，暴露并嵌入密封剂中用于焊球放置，其中顶部焊盘的焊接区域被定义 而不需要焊接掩模来解决在回流期间焊球在引线上的扩散。