公开(公告)号：US08250750B2

公开(公告)日：2012-08-28

申请号：US13019453

申请日：2011-02-02

Applicant: Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

Inventor： Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

IPC: H01K3/22

CPC classification number: H05K3/28 ,  H05K1/036 ,  H05K1/0393 ,  H05K3/101 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/0129 ,  H05K2201/0162 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/0759 ,  H05K2203/1105 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916

Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern, thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate tine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

Abstract translation: 根据本发明的制造带布线板的方法可以在形成布线图案中采用压印工艺，从而减少了用于制造带布线板的工艺的数量，并允许制造工艺在单个生产线中进行。 因此，制造时间和成本可能降低。 布线图案的轮廓可以通过模具的印模图案的形状来确定。 这可以建立内部和外部引线的顶部宽度并结合齿垫间距。 虽然ILB和OLB过程可能使用NCP，但是由于软和弹性布线图案可能建立连接可靠性。

公开(公告)号：US08114701B2

公开(公告)日：2012-02-14

申请号：US12274642

申请日：2008-11-20

Applicant: Woon-Seong Kwon ,  Tae-Je Cho ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Hyung-Sun Jang

Inventor： Woon-Seong Kwon ,  Tae-Je Cho ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Hyung-Sun Jang

IPC: H01L21/00

CPC classification number: H04N5/2252 ,  H01L27/14618 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H04N5/2253 ,  H04N5/2257 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: Provided are camera modules capable of effectively shielding electromagnetic (EM) waves and methods of fabricating the same. A method of fabricating a camera module includes, preparing a first wafer including an array of lens units. Then, a second wafer including an array of image sensor CSPs (chip-scale packages) is prepared. Each of the image sensor CSPs includes an image sensor chip corresponding to one of the lens units. The first wafer is stacked on the second wafer. The first wafer and the second wafer are cut to form a trench exposing the top surface of the image sensor chip at the interface between adjacent lens units. The trench is filled with a first material used for forming a housing. The first material and the image sensor chip are cut at the interface between the adjacent lens units.

Abstract translation: 提供能够有效屏蔽电磁波（EM）波的相机模块及其制造方法。 制造相机模块的方法包括：制备包括透镜单元阵列的第一晶片。 然后，制备包括图像传感器CSP阵列（芯片级封装）的第二晶片。 图像传感器CSP中的每一个包括对应于一个透镜单元的图像传感器芯片。 第一晶片被堆叠在第二晶片上。 切割第一晶片和第二晶片以形成在相邻透镜单元之间的界面处暴露图像传感器芯片的顶表面的沟槽。 沟槽填充有用于形成壳体的第一材料。 第一材料和图像传感器芯片在相邻透镜单元之间的界面处被切割。

公开(公告)号：US20090256931A1

公开(公告)日：2009-10-15

申请号：US12381489

申请日：2009-03-12

Applicant: Chung-Sun Lee ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Hyuek-Jae Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

Inventor： Chung-Sun Lee ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Hyuek-Jae Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

IPC: H04N5/76 ,  H01L21/50 ,  H04N5/225

CPC classification number: H04N5/2253 ,  H01L24/97 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/3025 ,  H04N5/2257 ,  H01L2924/00014

Abstract: A camera module, a method of manufacturing the same, and an electronic system having the same are provided. The camera module includes an image sensor chip having an active plane and a backside, a ground wiring extending from a sidewall of the image sensor chip to the backside, a lens structure having a light detector with at least one lens stacked on the active plane, and a conductive housing extending to the ground wiring along with an outer wall of the lens structure excluding the light detector.

Abstract translation: 提供了相机模块，其制造方法和具有该相机模块的电子系统。 相机模块包括具有活动平面和背面的图像传感器芯片，从图像传感器芯片的侧壁延伸到背面的接地布线，具有至少一个透镜的光检测器的透镜结构，该透镜结构堆叠在主动平面上， 以及与除了光检测器之外的透镜结构的外壁一起延伸到接地布线的导电外壳。

公开(公告)号：US20080284041A1

公开(公告)日：2008-11-20

申请号：US12045840

申请日：2008-03-11

Applicant: Hyung-sun JANG ,  Un-byoung KANG ,  Woon-seong KWON ,  Young-chai KWON ,  Chung-sun LEE ,  Dong-ho LEE

Inventor： Hyung-sun JANG ,  Un-byoung KANG ,  Woon-seong KWON ,  Young-chai KWON ,  Chung-sun LEE ,  Dong-ho LEE

IPC: H01L23/48

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14625 ,  H01L31/0203 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/01077 ,  H01L2924/14

Abstract: In a semiconductor package, an electrode has a first part extending through a semiconductor substrate and a second part extending from the first part through a compositional layer to reach a conductive pad.

Abstract translation: 在半导体封装中，电极具有延伸穿过半导体衬底的第一部分和从第一部分延伸通过组合层到达导电焊盘的第二部分。

公开(公告)号：US07299547B2

公开(公告)日：2007-11-27

申请号：US11086614

申请日：2005-03-21

Applicant: Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

Inventor： Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K3/28 ,  H05K1/036 ,  H05K1/0393 ,  H05K3/101 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/0129 ,  H05K2201/0162 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/0759 ,  H05K2203/1105 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916

Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern, thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate fine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

Abstract translation: 根据本发明的制造带布线板的方法可以在形成布线图案中采用压印工艺，从而减少了用于制造带布线板的工艺的数量，并允许制造工艺在单个生产线中进行。 因此，制造时间和成本可能降低。 布线图案的轮廓可以通过模具的印模图案的形状来确定。 这可以建立内部和外部引线的顶部宽度并且结合细小的垫间距。 虽然ILB和OLB过程可能使用NCP，但是由于软和弹性布线图案可能建立连接可靠性。

公开(公告)号：US07078331B2

公开(公告)日：2006-07-18

申请号：US10898445

申请日：2004-07-22

Applicant: Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee

Inventor： Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Provided are a method of forming a bump whose upper surface is substantially flat and whose area can be enlarged in a uniform pad pitch to simplify mounting a liquid crystal display drive IC (LDI) and a semiconductor chip and a mount structure using the method to minimize a pad area inside the chip. Thus, the pad area on an edge of a conventional chip is minimized and the bump is formed in a substantially flat location inside the chip and an electrical connection between the pad and the bump is performed by a redistribution metal line.

Abstract translation: 提供了一种形成凸起的方法，该凸块的上表面基本上是平的，并且其面积可以以均匀的垫间距扩大，以简化安装液晶显示驱动IC（LDI）和半导体芯片以及使用该方法的安装结构 芯片内部的焊盘区域。 因此，传统芯片的边缘上的焊盘区域被最小化，并且凸块形成在芯片内部的基本上平坦的位置，并且焊盘和凸块之间的电连接由再分布金属线执行。

公开(公告)号：US07895742B2

公开(公告)日：2011-03-01

申请号：US11872580

申请日：2007-10-15

Applicant: Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

Inventor： Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

IPC: H01K3/22

CPC classification number: H05K3/28 ,  H05K1/036 ,  H05K1/0393 ,  H05K3/101 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/0129 ,  H05K2201/0162 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/0759 ,  H05K2203/1105 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916

Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate fine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

Abstract translation: 根据本发明的制造带布线板的方法可以在形成布线图案中采用压印工艺，从而减少制造带布线板的工艺的数量，并允许制造工艺在单个生产线中进行。 因此，制造时间和成本可能降低。 布线图案的轮廓可以通过模具的印模图案的形状来确定。 这可以建立内部和外部引线的顶部宽度并且结合细小的垫间距。 虽然ILB和OLB过程可能使用NCP，但是由于软和弹性布线图案可能建立连接可靠性。

公开(公告)号：US20100320500A1

公开(公告)日：2010-12-23

申请号：US12870998

申请日：2010-08-30

Applicant: UN BYOUNG KANG ,  Yong Hwan Kwon ,  Chung Sun Lee ,  Woon Seong Kwon ,  Hyung Sun Jang

Inventor： UN BYOUNG KANG ,  Yong Hwan Kwon ,  Chung Sun Lee ,  Woon Seong Kwon ,  Hyung Sun Jang

IPC: H01L27/15 ,  H01L23/52 ,  H01L21/336

CPC classification number: H01L24/83 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11901 ,  H01L2224/11912 ,  H01L2224/13099 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/01007 ,  H01L2924/01028 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成扩散阻挡层，并在衬底上形成至少两个特征，使得扩散阻挡层分别设置在每个特征和衬底之间，并接触至少两个特征。 衬底的第一杂质区包含第一类杂质，衬底的第二杂质区包含不同于第一类型的第二类杂质，所述至少两个特征的第一特征在第一杂质区， 并且所述至少两个特征的第二特征在于第二杂质区域，使得第二特征通过不同的杂质区域与第一特征电隔离。

公开(公告)号：US07569423B2

公开(公告)日：2009-08-04

申请号：US12139771

申请日：2008-06-16

Applicant: Yong-hwan Kwon ,  Chung-sun Lee ,  Woon-byung Kang

Inventor： Yong-hwan Kwon ,  Chung-sun Lee ,  Woon-byung Kang

IPC: H01L21/48 ,  H01L23/34

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and side surfaces of the semiconductor substrate.

Abstract translation: 公开了一种晶片级芯片级封装及相关的制造方法。 晶片级芯片级封装包括半导体衬底，其包括集成电路，设置在半导体衬底上并与集成电路电连接的导电球，以及由绝缘材料形成并设置在底表面和侧表面上的保护部分 的半导体衬底。

公开(公告)号：US20090130791A1

公开(公告)日：2009-05-21

申请号：US12274642

申请日：2008-11-20

Applicant: Woon-Seong KWON ,  Tae-Je CHO ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

Inventor： Woon-Seong KWON ,  Tae-Je CHO ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

IPC: H01L21/00

CPC classification number: H04N5/2252 ,  H01L27/14618 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H04N5/2253 ,  H04N5/2257 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: Provided are camera modules capable of effectively shielding electromagnetic (EM) waves and methods of fabricating the same. A method of fabricating a camera module includes, preparing a first wafer including an array of lens units. Then, a second wafer including an array of image sensor CSPs (chip-scale packages) is prepared. Each of the image sensor CSPs includes an image sensor chip corresponding to one of the lens units. The first wafer is stacked on the second wafer. The first wafer and the second wafer are cut to form a trench exposing the top surface of the image sensor chip at the interface between adjacent lens units. The trench is filled with a first material used for forming a housing. The first material and the image sensor chip are cut at the interface between the adjacent lens units.

Abstract translation: 提供能够有效屏蔽电磁波（EM）波的相机模块及其制造方法。 制造相机模块的方法包括：制备包括透镜单元阵列的第一晶片。 然后，制备包括图像传感器CSP阵列（芯片级封装）的第二晶片。 图像传感器CSP中的每一个包括对应于一个透镜单元的图像传感器芯片。 第一晶片被堆叠在第二晶片上。 切割第一晶片和第二晶片以形成在相邻透镜单元之间的界面处暴露图像传感器芯片的顶表面的沟槽。 沟槽填充有用于形成壳体的第一材料。 第一材料和图像传感器芯片在相邻透镜单元之间的界面处被切割。