公开(公告)号：US06482730B1

公开(公告)日：2002-11-19

申请号：US09510084

申请日：2000-02-22

申请人： Mutsumi Masumoto ,  Kenji Masumoto

发明人： Mutsumi Masumoto ,  Kenji Masumoto

IPC分类号： H01L2144

CPC分类号： H01L24/12 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method to improve the resin sealing reliability in the manufacturing of a wafer-level CSP. The method for manufacturing a semiconductor device of the present invention includes a process that forms wiring 14 and conductive supports 16, which electrically connect electrode pads 10a and corresponding external terminals, on a wafer 10 on which semiconductor elements are formed. In subsequent processes, a groove 18 (preferably V shaped) is formed in the surface of the above-mentioned wafer along the boundary lines of the respective semiconductor elements. Next, the end surfaces of the above-mentioned conductive supports 16 are exposed, and the above-mentioned wafer surface is covered with a resin 19 so that external terminals 20 are arranged on the end surfaces of the conductive supports. In the final process, along the boundary lines of the above-mentioned semiconductor elements, packaged semiconductor devices 32 are obtained by dicing the above-mentioned wafer.

摘要翻译： 一种提高晶片级CSP制造中的树脂密封可靠性的方法。 本发明的半导体器件的制造方法包括在其上形成有半导体元件的晶片10上形成布线14和将电极焊盘10a和对应的外部端子电连接的导电支撑体16的工序。 在随后的处理中，沿着各个半导体元件的边界线，在上述晶片的表面中形成有槽18（优选为V形）。 接下来，将上述导电支撑体16的端面露出，上述晶片表面被树脂19覆盖，使得外部端子20布置在导电支撑件的端面上。 在最后的方法中，沿着上述半导体元件的边界线，通过切割上述晶片获得封装的半导体器件32。

公开(公告)号：US20120205354A1

公开(公告)日：2012-08-16

申请号：US13026376

申请日：2011-02-14

申请人： Takahiko Kudoh ,  Kenji Masumoto

发明人： Takahiko Kudoh ,  Kenji Masumoto

IPC分类号： B23K26/00

CPC分类号： B23K26/364 ,  B23K26/0006 ,  B23K26/08 ,  B23K26/1224 ,  B23K26/355 ,  B23K26/40 ,  B23K2101/34 ,  B23K2103/02 ,  B23K2103/04 ,  B23K2103/08 ,  B23K2103/12

摘要： A groove is formed in a metal sheet by performing an irradiation engraving operation on a first surface area of the metal sheet. The irradiation engraving operation displaces metal particles from the first surface area onto a second surface area of the metal sheet. The environment of the irradiation engraving operation is controlled to reduce the number of displaced metal particles that would otherwise weld to the second surface area.

摘要翻译： 通过在金属板的第一表面区域进行照射雕刻操作，在金属板中形成槽。 照射雕刻操作将金属颗粒从第一表面区域移位到金属片的第二表面区域上。 控制照射雕刻操作的环境以减少否则将焊接到第二表面区域的位移金属颗粒的数量。

公开(公告)号：US20110024899A1

公开(公告)日：2011-02-03

申请号：US12510781

申请日：2009-07-28

申请人： Kenji MASUMOTO ,  Masazumi Amagai ,  Masayuki Yoshino ,  Yukio Moriyama

发明人： Kenji MASUMOTO ,  Masazumi Amagai ,  Masayuki Yoshino ,  Yukio Moriyama

IPC分类号： H01L23/498 ,  H01L21/98

CPC分类号： H01L23/5389 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Various embodiments provide semiconductor devices having cavity substrate structures for package-on-package assembly and methods for their fabrication. In one embodiment, the cavity substrate structure can include at least one top interconnect via formed within a top substrate. The top substrate can be disposed over a base substrate having at least one base interconnect via that is not aligned with the top interconnect via. Semiconductor dies can be assembled in an open cavity of the top substrate and attached to a base center portion of the base substrate of the cavity substrate structure. A top semiconductor package can be mounted over the top substrate of the cavity substrate structure.

摘要翻译： 各种实施例提供了具有用于封装封装组件的空腔衬底结构的半导体器件及其制造方法。 在一个实施例中，空腔衬底结构可以包括在顶部衬底内形成的至少一个顶部互连通孔。 顶部衬底可以设置在具有至少一个基部互连的基底衬底上，该衬底不与顶部互连通孔对准。 半导体管芯可以组装在顶部衬底的开放空腔中并且附接到空腔衬底结构的基底衬底的基部中心部分。 顶部半导体封装可以安装在空腔衬底结构的顶部衬底上。

公开(公告)号：US07344916B2

公开(公告)日：2008-03-18

申请号：US11274433

申请日：2005-11-15

申请人： Kenji Masumoto

发明人： Kenji Masumoto

IPC分类号： H01L21/00

CPC分类号： H01L24/83 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512

摘要： A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond pads 351, and the second surface includes an array of solder balls 33. The device includes a semiconductor chip 30 having a top surface and a back surface, the back surface of the chip adjacent the interposer 31, and the top surface including a plurality of terminals. Also included is a layer of polymeric material 34 disposed on the first surface 311 of the interposer covering the area of the interposer over the solder ball array. At least a portion of the polymeric layer is between the chip 30 and the interposer 31. The device further includes a plurality of electrical connections 35 between the chip terminals and the bond pads 351 on the interposer.

摘要翻译： 半导体器件39.该器件包括具有两个主表面的中介层31。 第一表面311包括图案化金属导体和接合焊盘351，并且第二表面包括焊球33的阵列。该器件包括具有顶表面和后表面的半导体芯片30，芯片的背面邻近插入器 31，顶面包括多个端子。 还包括一层聚合材料34，其设置在插入件的第一表面311上，覆盖焊锡球阵列上的插入物的区域。 聚合物层的至少一部分在芯片30和插入件31之间。该器件还包括在芯片端子与插入器之间的接合焊盘351之间的多个电连接35。

公开(公告)号：US07005719B2

公开(公告)日：2006-02-28

申请号：US10788552

申请日：2004-02-27

申请人： Kenji Masumoto

发明人： Kenji Masumoto

IPC分类号： H01L31/0232

CPC分类号： G02B6/43 ,  G02B6/42 ,  G02B6/4201 ,  G02B6/4214 ,  G02B6/4232 ,  G02B6/4253 ,  G02B6/4257 ,  G02B6/426 ,  G02B6/428 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2224/16225 ,  H01L2924/15311

摘要： An apparatus comprising an integrated circuit structure is provided. The integrated circuit structure comprises a substrate and a photoreceiver. The substrate has a first side and a second side opposite the first side and includes a first light passage area operable to allow light to pass through. The photoreceiver has an aperture located on a first side of the photoreceiver and is flip-chip mounted to the substrate such that the first side of the photoreceiver faces the second side of the substrate. The photoreceiver is operable to translate light signals received through the aperture into digital signals and to transmit the digital signals. The first light passage area is aligned with the aperture of the photoreceiver such that the light signals may be received through the light passage area and into the aperture of the photoreceiver.

摘要翻译： 提供一种包括集成电路结构的装置。 集成电路结构包括基板和光接收器。 衬底具有与第一侧相对的第一侧和第二侧，并且包括可操作以允许光通过的第一光通过区域。 光接收器具有位于光接收器的第一侧上的孔，并且倒装芯片安装到基板，使得光接收器的第一侧面向基板的第二侧。 光接收器可操作以将通过孔接收的光信号转换为数字信号并传输数字信号。 第一光通过区域与光接收器的孔径对准，使得光信号可以通过光通过区域并且进入光接收器的孔径。

公开(公告)号：US06929971B2

公开(公告)日：2005-08-16

申请号：US10302254

申请日：2002-11-22

申请人： Kensho Murata ,  Mutsumi Masumoto ,  Kenji Masumoto

发明人： Kensho Murata ,  Mutsumi Masumoto ,  Kenji Masumoto

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L21/00

CPC分类号： H01L21/56 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/0508 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10234 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/13099

摘要： Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.

摘要翻译： 提高制造称为晶片级CSP的半导体器件的生产率和成本。 与本发明相关的半导体器件的制造方法包含形成布线（18）的每个工艺，其用于将每个电极焊盘（10a）和外部连接端子电连接到晶片（10）的顶部上， 形成半导体元件，连接通过其上的单独工艺预成型的导电球，接下来，用树脂（32）覆盖上述晶片，使得导电支撑柱（30）的上部暴露 。 在后面的处理中，焊球（34）被布置为导电支柱上部的外部连接端子，最后，通过沿着上述边界线对上述晶片进行切割而形成半导体元件 所述半导体元件。

公开(公告)号：US06835595B1

公开(公告)日：2004-12-28

申请号：US09744976

申请日：2001-06-04

申请人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

发明人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

IPC分类号： H01L2144

CPC分类号： H01L24/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

摘要翻译： 形成在与电极焊盘（2）一致的位置具有开口部（3a）的绝缘层（3）。 接着，在绝缘层（3）上形成树脂突起部（4）。 此后，形成抗蚀剂膜，其具有在与开口部分（3a），树脂突出部分（4）和夹在其间的区域相适应的区域中形成的开口部分。 通过使用抗蚀剂膜作为掩模，通过电解铜电镀形成Cu镀层（6）。