公开(公告)号：US07078331B2

公开(公告)日：2006-07-18

申请号：US10898445

申请日：2004-07-22

Applicant: Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee

Inventor： Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Provided are a method of forming a bump whose upper surface is substantially flat and whose area can be enlarged in a uniform pad pitch to simplify mounting a liquid crystal display drive IC (LDI) and a semiconductor chip and a mount structure using the method to minimize a pad area inside the chip. Thus, the pad area on an edge of a conventional chip is minimized and the bump is formed in a substantially flat location inside the chip and an electrical connection between the pad and the bump is performed by a redistribution metal line.

Abstract translation: 提供了一种形成凸起的方法，该凸块的上表面基本上是平的，并且其面积可以以均匀的垫间距扩大，以简化安装液晶显示驱动IC（LDI）和半导体芯片以及使用该方法的安装结构 芯片内部的焊盘区域。 因此，传统芯片的边缘上的焊盘区域被最小化，并且凸块形成在芯片内部的基本上平坦的位置，并且焊盘和凸块之间的电连接由再分布金属线执行。

公开(公告)号：US20060113648A1

公开(公告)日：2006-06-01

申请号：US11261260

申请日：2005-10-28

Applicant: Ye-Chung Chung ,  Dong-Han Kim ,  Sa-Yoon Kang

Inventor： Ye-Chung Chung ,  Dong-Han Kim ,  Sa-Yoon Kang

IPC: H01L23/02

CPC classification number: H01L23/49838 ,  H01L21/4839 ,  H01L23/49572 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor chip, having an active surface including a peripheral area and a central area, presents a connection area formed on a portion of the peripheral area. The semiconductor chip includes output pads formed in the peripheral area of the active surface and input pads formed in the central area of the active surface. The input pads may be connected to wiring patterns of a TAB tape passing over the connection area.

Abstract translation: 具有包括周边区域和中心区域的活性表面的半导体芯片具有形成在周边区域的一部分上的连接区域。 半导体芯片包括形成在有源表面的周边区域中的输出焊盘和形成在有源表面的中心区域中的输入焊盘。 输入焊盘可以连接到通过连接区域的TAB磁带的布线图案。

公开(公告)号：US20060012019A1

公开(公告)日：2006-01-19

申请号：US11173852

申请日：2005-06-30

Applicant: Suk-Chae Kang ,  Si-Hoon Lee ,  Sa-Yoon Kang ,  Dong-Han Kim ,  Yun-Hyeok Im ,  Gu-Sung Kim

Inventor： Suk-Chae Kang ,  Si-Hoon Lee ,  Sa-Yoon Kang ,  Dong-Han Kim ,  Yun-Hyeok Im ,  Gu-Sung Kim

IPC: H01L23/02

CPC classification number: H01L23/3675 ,  H01L23/13 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a semiconductor chip, a circuit board at which a wire pattern is formed, and a metal structure including a portion inserted through an opening of the circuit board and upon which the semiconductor chip rests. With the semiconductor chip in direct contact with the metal structure, thermal characteristics improve. With the circuit board supported by the metal structure, mechanical stability improves.

Abstract translation: 半导体封装包括半导体芯片，形成有线图形的电路板，以及包括插入电路板的开口部分的半导体芯片所在的金属结构体。 随着半导体芯片与金属结构直接接触，热特性得到改善。 由于电路板由金属结构支撑，机械稳定性提高。

公开(公告)号：US06903451B1

公开(公告)日：2005-06-07

申请号：US09723953

申请日：2000-11-27

Applicant: Nam Seog Kim ,  Dong Hyeon Jang ,  Sa Yoon Kang ,  Heung Kyu Kwon

Inventor： Nam Seog Kim ,  Dong Hyeon Jang ,  Sa Yoon Kang ,  Heung Kyu Kwon

IPC: H01L21/60 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L29/06 ,  H01L23/02

CPC classification number: H01L23/525 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

Abstract: In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer are provided. The reinforcing layer absorbs stress applied to the bumps when the CSP is mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.

Abstract translation: 根据本发明，在晶片级制造芯片级封装（CSP）。 CSP包括芯片，用于芯片的芯片焊盘重新分配的导体层，一个或两个绝缘层和多个凸起，其通过导体层互连到相应的芯片焊盘，并且是CSP的端子。 此外，为了提高CSP的可靠性，提供了增强层，边缘保护层和芯片保护层。 当CSP安装在电路板上并且长时间使用时，加强层吸收施加到凸起的应力，并延长凸块的寿命，从而延长CSP的寿命。 边缘保护层和芯片保护层防止外力损坏CSP。 在半导体晶片上形成构成CSP的所有元件之后，锯切半导体晶片以产生单独的CSP。

公开(公告)号：US20050040504A1

公开(公告)日：2005-02-24

申请号：US10862337

申请日：2004-06-08

Applicant: Sa-Yoon Kang ,  Dong-Han Kim ,  Ye-Chung Chung

Inventor： Sa-Yoon Kang ,  Dong-Han Kim ,  Ye-Chung Chung

IPC: H01L21/60 ,  G02F1/13 ,  G02F1/1345 ,  H01L23/538 ,  H05K1/11 ,  H05K1/14 ,  H01L23/02

CPC classification number: G02F1/13452 ,  H01L23/5387 ,  H01L2224/16 ,  H01L2924/07811 ,  H05K1/118 ,  H05K1/147 ,  H05K2201/068 ,  H05K2201/10681 ,  H01L2924/00

Abstract: Provided are a flexible film package module and a method of manufacturing the same that can be adapted for manufacture at lower cost and/or to adapt the characteristics of the flexible film package module for specific applications. The lower-cost flexible film package module includes a tape film that combines both a first insulating substrate, typically formed from a higher-cost polyimide material, and a second insulating substrate, typically formed from an insulating material or materials that are less expensive and/or provide modified performance when compared with the first insulating material. Both the first and second substrates will include complementary circuit patterns that will be electrically and physically connected to allow the composite substrate to function as a unitary substrate. The first and second substrates will also include connection regions that may be adapted for connection to printed circuit boards and/or electronic devices such as liquid crystal displays.

Abstract translation: 提供了一种柔性膜封装模块及其制造方法，其可以适于以更低成本制造和/或适应特定应用的柔性膜封装模块的特性。 较低成本的柔性膜封装模块包括一个胶带，其将通常由较高成本的聚酰亚胺材料形成的第一绝缘基板和通常由绝缘材料形成的第二绝缘基板或较便宜的材料和/ 或者与第一绝缘材料相比提供改进的性能。 第一和第二基板都将包括互补的电路图案，其将被电和物理连接，以允许复合基板作为整体基板。 第一和第二基板还将包括可适于连接到印刷电路板和/或诸如液晶显示器的电子设备的连接区域。

公开(公告)号：US06836018B2

公开(公告)日：2004-12-28

申请号：US10304264

申请日：2002-11-25

Applicant: Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

Inventor： Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

IPC: H01L2348

CPC classification number: H01L24/10 ,  H01L23/3157 ,  H01L23/34 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/3436 ,  H01L2924/00

Abstract: A thermal-stress-absorbing interface structure is provided between a semiconductor integrated circuit chip and a surface-mount structure. The interface structure comprises an elongated conductive-bump pad having a first length-wise end and a second length-wise end, and a side. The pad has an interconnection line extending from the side thereof intermediate the first and the second ends. The interconnection line is electrically connected to the chip. The interface structure further includes a first polymer layer having an exposed surface, and a second polymer layer, each having a different modulus of elasticity, disposed below the pad. The second polymer layer extends over substantially the entire exposed surface of the first polymer layer to absorb a thermal stress during thermal cycling.

Abstract translation: 在半导体集成电路芯片和表面安装结构之间提供热应力吸收界面结构。 界面结构包括具有第一纵向端和第二纵向端以及侧面的细长导电凸块垫。 垫具有从第一端和第二端的中间的一侧延伸的互连线。 互连线电连接到芯片。 界面结构还包括设置在垫下方的具有暴露表面的第一聚合物层和每个具有不同弹性模量的第二聚合物层。 第二聚合物层在第一聚合物层的基本上整个暴露的表面上延伸以在热循环期间吸收热应力。

公开(公告)号：US06818998B2

公开(公告)日：2004-11-16

申请号：US10157272

申请日：2002-05-28

Applicant: Yong Hwan Kwon ,  Se Yong Oh ,  Sa Yoon Kang

Inventor： Yong Hwan Kwon ,  Se Yong Oh ,  Sa Yoon Kang

IPC: H01L2334

CPC classification number: H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.

Abstract translation: 堆叠式芯片封装包括具有上表面和下表面的基板，具有上表面和下表面的第一半导体芯片，其中第一半导体芯片的下表面附着到基板的上表面，上表面 第一半导体芯片的表面包括多个第一电极焊盘和具有上表面和下表面的第二半导体芯片。 第二半导体芯片的下表面附接到第一半导体芯片的上表面，并且第二半导体芯片的下表面包括对应于第一半导体芯片的上表面上的第一电极焊盘的位置的沟槽 。

公开(公告)号：US06717272B2

公开(公告)日：2004-04-06

申请号：US10376110

申请日：2003-02-26

Applicant: Jin-Hyuk Lee ,  Sa-Yoon Kang ,  Dong-Whee Kwon ,  Ji-Yong You ,  Hye-Soo Shin

Inventor： Jin-Hyuk Lee ,  Sa-Yoon Kang ,  Dong-Whee Kwon ,  Ji-Yong You ,  Hye-Soo Shin

IPC: H01L2352

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05001 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device for reinforcing a substructure of a bond pad and a method for fabricating the same are provided. According to an embodiment, a semiconductor device for reinforcing a substructure of a bond pad comprises a semiconductor substrate and a substructure formed on the semiconductor substrate. The semiconductor device further includes an interlevel dielectric layer formed on the substructure. The interlevel dielectric layer includes a contact opening formed therein. The contact opening comprises a plurality of separate dots connected to each other. A contact plug is formed in the contact opening.

Abstract translation: 提供一种用于加强接合焊盘的子结构的半导体器件及其制造方法。 根据实施例，用于加强接合焊盘的子结构的半导体器件包括形成在半导体衬底上的半导体衬底和子结构。 半导体器件还包括形成在子结构上的层间电介质层。 层间电介质层包括形成在其中的接触开口。 接触开口包括彼此连接的多个分开的点。 接触插塞形成在接触开口中。

公开(公告)号：US06586275B2

公开(公告)日：2003-07-01

申请号：US10103630

申请日：2002-03-20

Applicant: Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

Inventor： Gu-Sung Kim ,  Dong-Hyeon Jang ,  Min-Young Son ,  Sa-Yoon Kang

IPC: H01L2144

CPC classification number: H01L24/10 ,  H01L23/3157 ,  H01L23/34 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/3436 ,  H01L2924/00

Abstract: A thermal-stress-absorbing interface structure between a semiconductor integrated circuit chip and a surface-mount structure and a method for manufacturing the same. The thermal-stress-absorbing interface structure comprises an elongated conductive-bump pad having a first length-wise end and a second length-wise end, and a side. The thermal-stress-absorbing interface structure includes means for allowing the first end of the pad to move up when the second end of the pad moves down and alternately allowing the first end to move down when the second end moves up, upon thermal cycling. The means has a center axis and the up-and-down movements of the pad are balanced on the center axis. In accordance with this novel structure of the present invention, interconnection reliability such as solder joint reliability can be significantly improved.

Abstract translation: 半导体集成电路芯片和表面安装结构之间的热应力吸收界面结构及其制造方法。 热应力吸收界面结构包括具有第一纵向端和第二纵向端以及侧面的细长导电凸块焊盘。 所述热应力吸收界面结构包括当所述垫的第二端向下移动时允许所述垫的第一端向上移动的装置，并且当热循环时，当所述第二端向上移动时交替允许所述第一端向下移动。 该装置具有中心轴线，并且垫片的上下运动在中心轴线上平衡。根据本发明的这种新颖结构，可以显着提高诸如焊点可靠性之类的互连可靠性。

公开(公告)号：US06448661B1

公开(公告)日：2002-09-10

申请号：US10059932

申请日：2002-01-28

Applicant: Hyeong-Seob Kim ,  Sa-Yoon Kang ,  Myung-Kee Chung ,  In-Ku Kang ,  Kwan-Jai Lee

Inventor： Hyeong-Seob Kim ,  Sa-Yoon Kang ,  Myung-Kee Chung ,  In-Ku Kang ,  Kwan-Jai Lee

IPC: H01L2348

CPC classification number: H01L24/83 ,  H01L23/481 ,  H01L24/29 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: A three-dimensional, multi-chip package with chip selection pads formed at the chip-level and a manufacturing method thereof are provided. The three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, (N−1) chip selection pads, an insulation layer, (N−1) metal wirings, upper connection terminals, lower connection terminals, and trench wirings. The chip selection terminal of each chip is separated from the chip selection of the other chips by the chip selection pads formed at the chip-level.

Abstract translation: 提供了一种具有在芯片级形成的芯片选择焊盘的三维多芯片封装及其制造方法。 通过堆叠多个（N）个半导体集成电路芯片来形成三维多芯片封装。 每个芯片包括集成电路管芯，芯片选择端子（N-1）芯片选择焊盘，绝缘层，（N-1）金属布线，上连接端子，下连接端子和沟槽布线。 每个芯片的芯片选择端通过在芯片级形成的芯片选择焊盘与其他芯片的芯片选择分离。