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43 条记录 (耗时 0.027 秒)

    Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires
    31.
    发明授权
    Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires 失效
    用于制造基于导电聚合物和半导体纳米线的塑料电子器件的完全集成的有机分层工艺

    公开(公告)号：US07345307B2

    公开(公告)日：2008-03-18

    申请号：US11233503

    申请日：2005-09-22

    申请人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

    发明人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

    IPC分类号： H01L29/10

    CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

    摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

    摘要翻译： 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

    Selective processing of semiconductor nanowires by polarized visible radiation
    33.
    发明授权
    Selective processing of semiconductor nanowires by polarized visible radiation 有权
    通过极化可见辐射选择性处理半导体纳米线

    公开(公告)号：US07786024B2

    公开(公告)日：2010-08-31

    申请号：US11936590

    申请日：2007-11-07

    申请人： David P. Stumbo ,  Yaoling Pan ,  Costas P. Grigoropoulos ,  Nipun Misra

    发明人： David P. Stumbo ,  Yaoling Pan ,  Costas P. Grigoropoulos ,  Nipun Misra

    IPC分类号： H01L21/00

    CPC分类号： H01L29/0665 ,  B23K26/073 ,  B82Y10/00 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/0673 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods, systems, and apparatuses for annealing semiconductor nanowires and for fabricating electrical devices are provided. Nanowires are deposited on a substrate. A plurality of electrodes is formed. The nanowires are in electrical contact with the plurality of electrodes. The nanowires are doped. A polarized laser beam is applied to the nanowires to anneal at least a portion of the nanowires. The nanowires may be aligned substantially parallel to an axis. The laser beam may be polarized in various ways to modify absorption of radiation of the applied laser beam by the nanowires. For example, the laser beam may be polarized in a direction substantially parallel to the axis or substantially perpendicular to the axis to enable different nanowire absorption profiles.

    摘要翻译： 提供了用于退火半导体纳米线并用于制造电气器件的方法，系统和装置。 纳米线沉积在基底上。 形成多个电极。 纳米线与多个电极电接触。 纳米线是掺杂的。 将极化激光束施加到纳米线以退火至少一部分纳米线。 纳米线可以基本上平行于轴线对准。 激光束可以以各种方式被极化，以通过纳米线来改变施加的激光束的辐射的吸收。 例如，激光束可以在基本上平行于轴线或基本上垂直于轴线的方向上极化，以实现不同的纳米线吸收曲线。

    Efficient thermal activation optical switch and method of making the same
    35.
    发明授权
    Efficient thermal activation optical switch and method of making the same 有权
    高效热激活光开关及其制作方法

    公开(公告)号：US06678435B2

    公开(公告)日：2004-01-13

    申请号：US09861120

    申请日：2001-05-18

    申请人： Yaoling Pan ,  Michele Palmieri ,  Richard E. Haven

    发明人： Yaoling Pan ,  Michele Palmieri ,  Richard E. Haven

    IPC分类号： G02B626

    CPC分类号： G02B6/3576 ,  G02B6/3538 ,  G02B6/3546 ,  G02B2006/12145

    摘要： An optical switch having an insulator under a heater element is disclosed. The insulator reduces the heat loss thereby making the switch more efficient. The insulator is fabricated embedded in the underlying substrate on which the heater and the optical intersection are fabricated. A method of fabricating the optical switch having an insulator is disclosed. A trench is etched on the substrate and filled with oxide or other suitable insulating material. Then, the heater and the optical intersection are fabricated above the insulator.

    摘要翻译： 公开了一种在加热器元件下方具有绝缘体的光开关。 绝缘体减少热损失，从而使开关更有效率。 制造的绝缘体嵌入在其上制造加热器和光学交叉点的下面的基板上。 公开了一种制造具有绝缘体的光开关的方法。 在衬底上蚀刻沟槽，并填充有氧化物或其它合适的绝缘材料。 然后，在绝缘体上方制造加热器和光学交叉点。

    Stacked vias for vertical integration
    37.
    发明授权
    Stacked vias for vertical integration 有权

    公开(公告)号：US10131534B2

    公开(公告)日：2018-11-20

    申请号：US13278080

    申请日：2011-10-20

    申请人： Yaoling Pan ,  Lixia Zhou

    发明人： Yaoling Pan ,  Lixia Zhou

    IPC分类号： G09G5/00 ,  B81B7/00 ,  B81C1/00

    摘要： This disclosure provides systems, methods and apparatus for a via structure. In one aspect, an apparatus includes a substrate and a first electromechanical systems device on a surface of the substrate. The first electromechanical systems device includes a first metal layer and a second metal layer. A first via structure can be included on the surface of the substrate. The first via structure includes the first metal layer, the second metal layer, and a third metal layer. The first metal layer of the first electromechanical systems device may be the same metal layer as the first metal layer of the first via structure.

    THIN FILM STACK WITH SURFACE-CONDITIONING BUFFER LAYERS AND RELATED METHODS
    38.
    发明申请
    THIN FILM STACK WITH SURFACE-CONDITIONING BUFFER LAYERS AND RELATED METHODS 有权
    具有表面调节缓冲层的薄膜堆叠及相关方法

    公开(公告)号：US20140036340A1

    公开(公告)日：2014-02-06

    申请号：US13565688

    申请日：2012-08-02

    申请人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

    发明人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

    IPC分类号： G02B26/00 ,  C23C16/44

    CPC分类号： G02B26/001

    摘要： This disclosure provides systems, methods and apparatus for a thin film stack with surface-conditioning buffer layers. In one aspect, the thin film stack includes a plurality of thin film layers each having a thickness greater than about 10 nm and a plurality of surface-conditioning buffer layers each having a thickness between about 1 nm and about 10 nm. The surface-conditioning buffer layers are alternatingly disposed between the thin film layers. Each of the surface-conditioning buffer layers are formed with the same or substantially the same thickness and composition. In some implementations, the surface-conditioning buffer layers are formed by atomic layer deposition.

    摘要翻译： 本公开提供了具有表面调节缓冲层的薄膜堆叠的系统，方法和装置。 在一个方面，薄膜堆叠包括多个厚度大于约10nm的薄膜层以及各自具有约1nm至约10nm厚度的多个表面调节缓冲层。 表面调节缓冲层交替地设置在薄膜层之间。 每个表面调节缓冲层以相同或基本上相同的厚度和组成形成。 在一些实施方案中，表面调节缓冲层通过原子层沉积形成。

    METHOD AND APPARATUS FOR WAFER-LEVEL SOLDER HERMETIC SEAL ENCAPSULATION OF MEMS DEVICES
    39.
    发明申请
    METHOD AND APPARATUS FOR WAFER-LEVEL SOLDER HERMETIC SEAL ENCAPSULATION OF MEMS DEVICES 审中-公开
    MEMS器件的水平焊缝密封封装的方法和装置

    公开(公告)号：US20130119489A1

    公开(公告)日：2013-05-16

    申请号：US13294831

    申请日：2011-11-11

    申请人： Tallis Y. Chang ,  Yaoling Pan ,  John H. Hong ,  Chong U. Lee

    发明人： Tallis Y. Chang ,  Yaoling Pan ,  John H. Hong ,  Chong U. Lee

    IPC分类号： H01L31/18 ,  H01L31/0203

    CPC分类号： B81C1/00293 ,  B81C2203/0145

    摘要： A plurality of MEMS devices are formed on a substrate, a sacrificial layer is formed to cover each of the MEMS devices and a protective cap layer is formed on the sacrificial layer. A release hole is formed through the protective cap layer to the underlying sacrificial layer, and a releasing agent is introduced through the release hole to remove the sacrificial layer under the protective cap layer and expose a MEMS device. Optionally, the MEMS device can be released with the same releasing agent or, optionally, with a secondary releasing agent. The release hole is solder sealed, to form a hermetic seal of the MEMS device. Optionally, release holes are formed at a plurality of locations, each over a MEMS device and the releasing forms a plurality of hermetic sealed MEMS devices on the wafer substrate, which are singulated to form separate hermetically sealed MEMS devices.

    摘要翻译： 在衬底上形成多个MEMS器件，形成牺牲层以覆盖每个MEMS器件，并且在牺牲层上形成保护帽层。 通过保护盖层形成释放孔到下面的牺牲层，并且通过释放孔引入脱模剂以除去保护盖层下面的牺牲层并暴露MEMS器件。 可选地，MEMS器件可以用相同的脱模剂或任选地与二次释放剂一起释放。 释放孔被焊接密封，以形成MEMS器件的气密密封。 可选地，在多个位置上形成释放孔，每个位置都在MEMS器件上，并且释放在晶片衬底上形成多个密封的MEMS器件，其被单个化以形成分开的密封的MEMS器件。