公开(公告)号：US20110177435A1

公开(公告)日：2011-07-21

申请号：US12690312

申请日：2010-01-20

Applicant: Russell T. Herrin ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Russell T. Herrin ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: G03F1/00

CPC classification number: G03F1/42 ,  G03F1/36 ,  G03F1/38

Abstract: A photomask that is used as a light filter in an exposure system is made of at least one layer of material comprising one or more transparent regions and one or more non-transparent regions. The difference between the transparent regions and the non-transparent regions defines the features that will be illuminated by the exposure system on a photoresist that will be exposed using the exposure system. The features comprise one or more device shapes and at least one sub-lithographic shape that will be exposed upon the photoresist. The sub-lithographic shape has an sub-lithographic shape size that is limited in such a way that the sub-lithographic shape causes a physical change only in a surface of the photoresist. Therefore, because the sub-lithographic shape is so small, it avoids forming an opening through the photoresist after the photoresist is developed and only causes a change on the surface of the photoresist.

Abstract translation: 在曝光系统中用作滤光器的光掩模由包括一个或多个透明区域和一个或多个不透明区域的至少一层材料制成。 透明区域和不透明区域之间的差异限定了曝光系统将在将使用曝光系统曝光的光刻胶上照亮的特征。 这些特征包括一个或多个器件形状和将被暴露在光刻胶上的至少一个亚光刻形状。 亚光刻形状具有亚光刻形状尺寸，其受到限制，使得亚光刻形状仅在光致抗蚀剂的表面引起物理变化。 因此，由于亚光刻形状如此之小，因此避免了在光致抗蚀剂显影之后通过光致抗蚀剂形成开口，并且仅引起光致抗蚀剂表面的变化。

公开(公告)号：US07964967B2

公开(公告)日：2011-06-21

申请号：US12046737

申请日：2008-03-12

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/02 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.

Abstract translation: 用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。 接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

公开(公告)号：US20110057319A1

公开(公告)日：2011-03-10

申请号：US12555981

申请日：2009-09-09

Applicant: Donald R. Dean, JR. ,  Peter J. Lindgren ,  Glen L. Miles ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Donald R. Dean, JR. ,  Peter J. Lindgren ,  Glen L. Miles ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L23/48 ,  G06F17/50

CPC classification number: H01L21/76898 ,  G06F17/5072

Abstract: A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.

Abstract translation: 评估包括多个贯穿硅通孔（TSV）的IC布局的一部分以识别线性对准的TSV。 修改IC布局的部分以减少多个线性对齐的TSV，导致较少的晶片断裂。

公开(公告)号：US20100155936A1

公开(公告)日：2010-06-24

申请号：US12342393

申请日：2008-12-23

Applicant: Steven R. Codding ,  Timothy C. Krywanczyk ,  Timothy E. Neary ,  Edmund J. Sprogis

Inventor： Steven R. Codding ,  Timothy C. Krywanczyk ,  Timothy E. Neary ,  Edmund J. Sprogis

IPC: H01L21/30 ,  H01L23/488

CPC classification number: H01L21/6835 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/27436 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/09701 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical support to enable thinning of the semiconductor substrate to a thickness of about 25 μm. A film frame tape is attached to the back side of the thinned semiconductor substrate and the laser-ablative adhesive layer is ablated by laser, thereby dissociating the carrier substrate from the back side of the C4 grind tape. The assembly of the film frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. The C4 grind tape is irradiated by ultraviolet light to become less adhesive, and is subsequently removed.

Abstract translation: 在半导体基板的正面上形成C4研磨胶带和激光烧蚀粘合剂层。 然后将载体基板连接到激光烧蚀粘合剂层。 通过抛光或研磨使半导体衬底的背面变薄，在此期间，载体衬底提供机械支撑以使半导体衬底的薄化能够达到约25μm的厚度。 胶片框架胶带附着到减薄的半导体衬底的背面，激光烧蚀粘合剂层通过激光烧蚀，从而使载体衬底与C4研磨胶带的背面分离。 薄膜框架胶带，变薄的半导体衬底和C4研磨胶带的组装被切割。 通过紫外线照射C4研磨胶带以变得粘合性变差，随后被除去。

公开(公告)号：US07719118B2

公开(公告)日：2010-05-18

申请号：US11838917

申请日：2007-08-15

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Edmund J. Sprogis

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/3157 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.

Abstract translation: 形成有可以与衬底隔离或电连接的通孔形成的半导体芯片级封装以及可以隔离或电连接到衬底的具有通孔的半导体芯片级封装的方法。

公开(公告)号：US07683478B2

公开(公告)日：2010-03-23

申请号：US12026776

申请日：2008-02-06

Applicant: Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

Inventor： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

IPC: H01L23/34

CPC classification number: H01L25/50 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

Abstract translation: 一种密封的微电子结构，其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。 每个芯片沿着其周边包括连续的接合材料，以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。 每个支撑柱向外延伸，使得当至少两个芯片彼此定位时，支撑柱彼此配合。 至少两个芯片之间的密封由芯片彼此的重叠关系产生，使得接合材料和支撑柱彼此配合。 因此，当至少两个芯片配合在一起时形成密封，并且导致粘合芯片结构。

公开(公告)号：US20100019346A1

公开(公告)日：2010-01-28

申请号：US12180810

申请日：2008-07-28

Applicant: Mete Erturk ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Mete Erturk ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L29/00

CPC classification number: H01L24/91 ,  H01F17/0006 ,  H01F27/027 ,  H01L23/645 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/73257 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2224/05599 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: IC and design structure including various ways of raising a passive element such as an inductor off the surface of the substrate to improve the performance of the passive element are presented. A first wafer may be provided, and passive elements diced from a second wafer. The passive elements are flipped, and then aligned to be bonded on the first wafer such that the passive elements are raised a distance off the first wafer because of the presence of chip connections such as C4 solder bumps. A gap between the passive elements and the first wafer can be filled with underfill or air. If air is used, a hermetic seal around the gap can be created using chip connections such as C4 solder bumps or other known bonding means to seal the gap.

Abstract translation: 提出了IC和设计结构，其中包括从基板表面起提高无源元件（如电感器）以提高无源元件的性能的各种方式。 可以提供第一晶片，并且从第二晶片切割无源元件。 无源元件翻转，然后对齐以接合在第一晶片上，使得无源元件由于存在诸如C4焊料凸块的芯片连接而离开第一晶片一段距离。 无源元件和第一晶片之间的间隙可以用底部填充物或空气填充。 如果使用空气，则可以使用诸如C4焊料凸块或其它已知的粘合装置之类的芯片连接来密封间隙来创建间隙周围的气密密封。

公开(公告)号：US20090206407A1

公开(公告)日：2009-08-20

申请号：US12033280

申请日：2008-02-19

Applicant: Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Edmund J. Sprogis

Inventor： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Edmund J. Sprogis

IPC: H01L29/78 ,  H01L21/762

CPC classification number: H01L21/823807 ,  H01L21/76205 ,  H01L21/823878 ,  H01L29/7846

Abstract: A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.

Abstract translation: 公开了一种半导体器件和制造方法，其具有施加到其上的拉伸和/或压缩应变。 该方法包括在材料中形成至少一个沟槽; 以及通过氧化工艺填充所述至少一个沟槽，从而在器件的通道中形成应变集中。 该结构包括分别在第一通道上具有沟道和第一氧化沟槽的栅极结构。 第一氧化沟槽在通道中产生应变分量以增加器件性能。

公开(公告)号：US20090124047A1

公开(公告)日：2009-05-14

申请号：US12353549

申请日：2009-01-14

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L21/70

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US07498236B2

公开(公告)日：2009-03-03

申请号：US11563715

申请日：2006-11-28

Applicant: Steven R. Codding ,  Timothy C. Krywanczyk ,  Edmund J. Sprogis

Inventor： Steven R. Codding ,  Timothy C. Krywanczyk ,  Edmund J. Sprogis

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/306 ,  C23F1/00

CPC classification number: H01L21/78

Abstract: Disclosed are a method of and system for fabricating a semiconductor wafer. The method comprises the steps of providing a silicon wafer having a front side an a back side, building an integrated circuit on the front side of the wafer, and thereafter removing substrate from the back side of the silicon wafer. The building step includes the steps of forming a desired structure in the wafer, and forming an end structure in the wafer, said end structure extending to a greater depth, toward the back side of the wafer, than the desired structure. Also, the removing step includes the step of removing said substrate only to the end structure, whereby no part of the desired structure is removed during the removing step.

Abstract translation: 公开了用于制造半导体晶片的方法和系统。 该方法包括以下步骤：提供具有正面和背面的硅晶片，在晶片前侧构建集成电路，然后从硅晶片的背面去除衬底。 构建步骤包括以下步骤：在晶片中形成期望的结构，并且在晶片中形成端部结构，所述端部结构延伸到比晶片的背面更大的深度，而不是期望的结构。 此外，除去步骤包括仅将该基材除去至端部结构的步骤，由此在除去步骤期间不除去所需结构的一部分。