公开(公告)号：US20120282768A1

公开(公告)日：2012-11-08

申请号：US13551500

申请日：2012-07-17

申请人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

发明人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/322 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

摘要翻译： 形成半导体结构的方法包括提供基板; 在衬底上形成低k电介质层; 将导电布线嵌入到低k电介质层中; 并且将导电布线热浸在含碳硅烷类化学品中以在导电布线上形成阻挡层。 在用于嵌入导电布线的开口中形成衬里阻挡层。 衬里阻挡层可以包括与阻挡层相同的材料，并且衬里阻挡层可以在形成阻挡层之前被凹入，并且可以包含可以被硅化的金属。

公开(公告)号：US07564136B2

公开(公告)日：2009-07-21

申请号：US11361331

申请日：2006-02-24

申请人： Ming Ling Yeh ,  Chen-Hua Yu ,  Keng-Chu Lin ,  Tien-I Bao ,  Shwang-Ming Cheng

发明人： Ming Ling Yeh ,  Chen-Hua Yu ,  Keng-Chu Lin ,  Tien-I Bao ,  Shwang-Ming Cheng

IPC分类号： H01L23/48

CPC分类号： H01L21/76834 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846

摘要： A semiconductor structure having an opening formed in a porous dielectric layer is provided. The exposed pores of the dielectric layer along the sidewalls of the opening are sealed. The sealing may comprise a selective or a non-selective deposition method. The sealing layer has a substantially uniform thickness in one portion of the opening and a non-uniform thickness in another portion of the opening. A damascene interconnect structure having a pore sealing layer is provided as is its method of manufacture.

摘要翻译： 提供了一种形成在多孔电介质层中的开口的半导体结构。 沿着开口的侧壁的电介质层的暴露的孔被密封。 密封可以包括选择性或非选择性沉积方法。 密封层在开口的一部分中具有基本均匀的厚度，并且在开口的另一部分中具有不均匀的厚度。 如其制造方法那样提供具有孔密封层的镶嵌互连结构。

公开(公告)号：US20070278682A1

公开(公告)日：2007-12-06

申请号：US11509498

申请日：2006-08-24

申请人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

发明人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect structure of an integrated circuit includes a low-k dielectric layer over a semiconductor substrate, a conductor in the low-k dielectric layer, and a dielectric transition layer between the low-k dielectric layer and the conductor, wherein the dielectric transition layer has a thickness of less than about 50 Å.

摘要翻译： 集成电路的互连结构包括半导体衬底上的低k电介质层，低k电介质层中的导体和低k电介质层与导体之间的介电过渡层，其中介电转移层 具有小于约50埃的厚度。

公开(公告)号：US20140021614A1

公开(公告)日：2014-01-23

申请号：US13554817

申请日：2012-07-20

申请人： Chen-Hua Yu ,  Tien-I Bao

发明人： Chen-Hua Yu ,  Tien-I Bao

IPC分类号： H01L23/485 ,  H01L21/28

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.

摘要翻译： 器件包括第一低k电介质层和第一低k电介质层中的含铜通孔。 该器件还包括位于第一低k电介质层上的第二低k电介质层和在含铜通孔上电耦合的含铝金属线。 含铝金属线在第二低k电介质层中。

公开(公告)号：US20120289062A1

公开(公告)日：2012-11-15

申请号：US13562101

申请日：2012-07-30

申请人： Ching-Yu Lo ,  Hung-Jung Tu ,  Hai-Ching Chen ,  Tien-I Bao ,  Wen-Chih Chiou ,  Chen-Hua Yu

发明人： Ching-Yu Lo ,  Hung-Jung Tu ,  Hai-Ching Chen ,  Tien-I Bao ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC分类号： H01L21/71

CPC分类号： H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L2221/68372 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.

摘要翻译： 集成电路结构包括半导体衬底; 贯穿半导体衬底的贯通半导体通孔（TSV）开口; 和TSV开口的TSV衬管。 TSV衬套包括在TSV开口的侧壁上的侧壁部分和TSV开口底部的底部。 TSV衬管的底部部分的底部高度大于TSV衬套的侧壁部分的中间厚度。

公开(公告)号：US08030781B2

公开(公告)日：2011-10-04

申请号：US12233974

申请日：2008-09-19

申请人： Chen-Hua Yu ,  Tien-I Bao

发明人： Chen-Hua Yu ,  Tien-I Bao

IPC分类号： H01L23/485

CPC分类号： H01L24/05 ,  H01L23/5226 ,  H01L24/06 ,  H01L24/45 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05097 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48666 ,  H01L2224/48684 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48766 ,  H01L2224/48784 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48866 ,  H01L2224/48881 ,  H01L2224/48884 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2224/48744 ,  H01L2224/48781 ,  H01L2224/48681

摘要： A semiconductor structure is provided. In one embodiment, a bond pad is formed above one or more underlying layers of a substrate. A plurality of dummy plugs are spaced around the bond pad, the plurality of dummy plugs substantially vertically traversing the one or more underlying layers, wherein the plurality of dummy plugs anchor at least two of the underlying layers together to achieve improved mechanical strength.

摘要翻译： 提供半导体结构。 在一个实施例中，在衬底的一个或多个下层上方形成接合焊盘。 多个虚拟插头围绕接合焊盘间隔开，多个虚拟插头基本垂直地穿过一个或多个下层，其中多个虚拟插头将至少两个下面的层固定在一起以实现改进的机械强度。

公开(公告)号：US20110223762A1

公开(公告)日：2011-09-15

申请号：US13115161

申请日：2011-05-25

申请人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

发明人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L21/283

CPC分类号： H01L23/53238 ,  H01L21/322 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

摘要翻译： 形成半导体结构的方法包括提供基板; 在衬底上形成低k电介质层; 将导电布线嵌入到低k电介质层中; 并且将导电布线热浸在含碳硅烷类化学品中以在导电布线上形成阻挡层。 在用于嵌入导电布线的开口中形成衬里阻挡层。 衬里阻挡层可以包括与阻挡层相同的材料，并且衬里阻挡层可以在形成阻挡层之前被凹入，并且可以包含可以被硅化的金属。

公开(公告)号：US07968451B2

公开(公告)日：2011-06-28

申请号：US12509039

申请日：2009-07-24

申请人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

发明人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

IPC分类号： H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.

摘要翻译： 一种用于制造集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，并且用气体有机化学品处理低k电介质层以引起第 低k电介质层和气态有机化学品。 气态有机化学物质不含硅。

公开(公告)号：US07964496B2

公开(公告)日：2011-06-21

申请号：US11602808

申请日：2006-11-21

申请人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

发明人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/322 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

摘要翻译： 形成半导体结构的方法包括提供基板; 在衬底上形成低k电介质层; 将导电布线嵌入到低k电介质层中; 并且将导电布线热浸在含碳硅烷类化学品中以在导电布线上形成阻挡层。 在用于嵌入导电布线的开口中形成衬里阻挡层。 衬里阻挡层可以包括与阻挡层相同的材料，并且衬里阻挡层可以在形成阻挡层之前被凹入，并且可以包含可以被硅化的金属。

公开(公告)号：US20090286394A1

公开(公告)日：2009-11-19

申请号：US12509039

申请日：2009-07-24

申请人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

发明人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L21/306

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.

摘要翻译： 一种用于制造集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，并且用气体有机化学品处理低k电介质层以引起第 低k电介质层和气态有机化学品。 气态有机化学物质不含硅。