公开(公告)号：US20140232010A1

公开(公告)日：2014-08-21

申请号：US13770464

申请日：2013-02-19

Applicant: GLOBALFOUNDRIES, INC.

Inventor： San Leong Liew ,  Huang Liu

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods of forming integrated circuits are provided. A method of forming an integrated circuit includes providing a substrate that includes an electrical contact disposed therein. A first dielectric layer is formed over the substrate and electrical contact. A metal-containing layer is patterned over the first dielectric layer, with at least a first portion of the patterned metal-containing layer disposed over the first dielectric layer. The patterned metal-containing layer is absent in regions of the first dielectric layer over the electrical contact. A second dielectric layer is formed over the patterned metal-containing layer. A first via is etched in the first dielectric layer and the second dielectric layer over the electrical contact, and a second via is etched in the second dielectric layer over the patterned metal-containing layer. The first via and the second via are filled with an electrically-conductive material.

Abstract translation: 提供了形成集成电路的集成电路和方法。 形成集成电路的方法包括提供包括设置在其中的电接触的基板。 第一电介质层形成在衬底上并进行电接触。 在第一介电层上图案化含金属层，其中图案化的含金属层的至少第一部分设置在第一介电层上。 在电触点上的第一介电层的区域中不存在图案化的含金属层。 在图案化的含金属层上形成第二介电层。 在第一电介质层和第二电介质层上蚀刻第一通孔，并且在图案化的含金属层上的第二介电层中蚀刻第二通孔。 第一通孔和第二通孔被填充有导电材料。

公开(公告)号：US08716150B1

公开(公告)日：2014-05-06

申请号：US13860603

申请日：2013-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo Sun ,  Songkram Srivathanakul ,  Huang Liu ,  Hung-Wei Liu

IPC: H01L21/469 ,  H01L21/31

CPC classification number: H01L21/3105 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/0234

Abstract: Methods of forming a semiconductor device are provided. The methods include, for example, forming a low-k dielectric having a continuous planar surface, and, after forming the low-k dielectric, subjecting the continuous planar surface of the low-k dielectric to an ethylene plasma enhanced chemical vapor deposition (PECVD) treatment.

Abstract translation: 提供了形成半导体器件的方法。 所述方法包括例如形成具有连续平坦表面的低k电介质，并且在形成低k电介质之后，使低k电介质的连续平面表面经受乙烯等离子体增强化学气相沉积（PECVD ）治疗。

公开(公告)号：US10910471B2

公开(公告)日：2021-02-02

申请号：US16032878

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Sang Woo Lim ,  Matthew Wahlquist Stoker ,  Huang Liu ,  Jinping Liu

IPC: H01L29/76 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3× fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3× fin pitch, a TS formed on the RSD, and an ILD formed over the TS.

公开(公告)号：US10854472B2

公开(公告)日：2020-12-01

申请号：US14219039

申请日：2014-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huang Liu ,  Wen-Pin Peng ,  Jean-Baptiste Laloe

IPC: H01L21/312 ,  H01L21/321 ,  H01L29/66 ,  H01L27/092 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/78 ,  H01L29/49 ,  H01L21/768

Abstract: Aspects of the present invention relate to approaches for forming a semiconductor device such as a field-effect-transistor (FET) having a metal gate with improved performance. A metal gate is formed on a substrate in the semiconductor device. Further processing can result in unwanted oxidation in the metal that forms the metal gate. A reducing agent can be used to de-oxidize the metal that forms the metal gate, leaving a substantially non-oxidized surface.

公开(公告)号：US09754837B1

公开(公告)日：2017-09-05

申请号：US15160409

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Jinping Liu ,  Huang Liu ,  Taifong Chao

IPC: H01L29/15 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7856

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a mask over an oxide layer and an underlying set of fin structures, the set of fin structures including a plurality of fins each having a substrate base and a silicide layer over the substrate base; implanting the oxide layer through an opening in the mask; removing the mask; polishing the oxide layer overlying the set of fin structures after removing the mask to expose the set of fin structures; and forming a nitride layer over the set of fin structures.

公开(公告)号：US09620380B1

公开(公告)日：2017-04-11

申请号：US14972804

申请日：2015-12-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xintuo Dai ,  Huang Liu ,  Jin Ping Liu ,  Jiong Li

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/033 ,  H01L27/108

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/10826 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method for fabricating an integrated circuit includes providing an semiconductor wafer includes forming in an upper mandrel layer a first upper mandrel having a first critical dimension and a second upper mandrel having a second critical dimension; forming upper sidewall spacers along sidewalls of the first upper mandrel while leaving the second upper mandrel without sidewall spacers; removing the first upper mandrel from between the upper sidewall spacers; transferring a pattern of the upper sidewall spacers and of the second upper mandrel into a lower mandrel layer to form first lower mandrels according to the pattern of the upper sidewall spacers and a second lower mandrel according to the pattern of the second upper mandrel; and forming lower sidewall spacers along sidewalls of the first and second lower mandrels.

公开(公告)号：US09466723B1

公开(公告)日：2016-10-11

申请号：US14751718

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Qiang Fang ,  Jin Ping Liu ,  Huang Liu

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L21/283 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L29/7851 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes forming a placeholder source/drain contact structure above a semiconductor material. A conformal deposition process is performed to form a liner layer above the placeholder contact structure. A dielectric layer is formed above the liner layer. A first planarization process is performed to remove material of the dielectric layer and expose a first top surface of the liner layer above the placeholder contact structure. A first cap layer is formed above the dielectric layer. A second planarization process is performed to remove material of the first cap layer and the liner layer to expose a second top surface of the placeholder contact structure. The placeholder contact structure is removed to define a source/drain contact recess in the dielectric layer. The sidewalls of the dielectric layer in the source/drain contact recess are covered by the liner layer. A conductive material is formed in the contact recess.

Abstract translation: 一种方法包括在半导体材料之上形成占位符源极/漏极接触结构。 执行保形沉积工艺以在占位符接触结构之上形成衬垫层。 在衬层上方形成介电层。 执行第一平面化处理以去除电介质层的材料并将衬垫层的第一顶表面暴露在占位符接触结构之上。 在电介质层上方形成第一盖层。 执行第二平面化处理以去除第一盖层和衬垫层的材料以暴露占位符接触结构的第二顶表面。 去除占位符接触结构以在电介质层中限定源极/漏极接触凹部。 源极/漏极接触凹部中的电介质层的侧壁被衬里层覆盖。 导电材料形成在接触凹部中。

公开(公告)号：US09385192B2

公开(公告)日：2016-07-05

申请号：US14810167

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

公开(公告)号：US09324841B2

公开(公告)日：2016-04-26

申请号：US14049848

申请日：2013-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Hyucksoo Yang ,  Huang Liu ,  Richard J. Carter

IPC: H01L21/20 ,  H01L21/336 ,  H01L29/76 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66795 ,  H01L21/8238 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase carrier mobility. However, subsequent processes such as deposition of flowable oxide and annealing can damage the stressor regions, diminishing the amount of stress that is induced. Embodiments of the present invention provide a protective layer of silicon or silicon oxide over the stressor regions prior to the flowable oxide deposition and anneal.

Abstract translation: 本发明的实施例提供了用于制造诸如finFET的场效应晶体管的改进方法。 应力区域用于增加载流子迁移率。 然而，诸如沉积可流动氧化物和退火的后续过程可能损害应力区域，减少了所引起的应力量。 本发明的实施例在可流动的氧化物沉积和退火之前在应力区域上提供硅或氧化硅的保护层。

公开(公告)号：US09318440B2

公开(公告)日：2016-04-19

申请号：US14799116

申请日：2015-07-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Songkram Srivathanakul ,  Huang Liu ,  Garo Jacques Derderian ,  Boaz Alperson

IPC: H01L21/4763 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5329 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material having a set carbon content conformally within the at least one contact opening disposed over the semiconductor substrate.

Abstract translation: 提供电路结构的导电接触结构及其制造方法。 该制造包括例如提供设置在半导体衬底上的至少一个接触开口; 在所述半导体衬底上设置的所述至少一个接触开口中形成具有固定碳含量的富碳接触衬垫材料。