公开(公告)号：US20160343659A1

公开(公告)日：2016-11-24

申请号：US14718502

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L23/525 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L23/5256 ,  H01L21/84 ,  H01L27/1203

Abstract: A method of forming a semiconductor device comprising a fuse is provided including providing a semiconductor-on-insulator (SOI) structure comprising an insulating layer and a semiconductor layer formed on the insulating layer, forming raised semiconductor regions on the semiconductor layer adjacent to a central portion of the semiconductor layer and performing a silicidation process of the central portion of the semiconductor layer and the raised semiconductor regions to form a silicided semiconductor layer and silicided raised semiconductor regions.

Abstract translation: 提供一种形成包括熔丝的半导体器件的方法，包括：提供绝缘层上的绝缘体上半导体结构（SOI）结构和形成在绝缘层上的半导体层，在与中心相邻的半导体层上形成凸起的半导体区域 并且对半导体层的中心部分和凸起的半导体区域进行硅化处理，以形成硅化半导体层和硅化凸起的半导体区域。

公开(公告)号：US09461145B2

公开(公告)日：2016-10-04

申请号：US14503810

申请日：2014-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Jan Hoentschel ,  Martin Gerhardt

IPC: H01L21/3213 ,  G03F1/36 ,  H01L29/66 ,  H01L21/762 ,  H01L29/165 ,  H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  G03F1/72 ,  H01L21/033

CPC classification number: H01L29/66545 ,  G03F1/72 ,  H01L21/02164 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI region in a silicon substrate, the STI region having a top width; and forming a dummy electrode on the STI region and a gate electrode on the silicon substrate, the dummy electrode having a width greater than or equal to the STI region top width.

Abstract translation: 通过OPC切割掩模校正将虚拟电极放大到STI顶部宽度尺寸，并且公开了所得到的器件。 实施例包括在硅衬底中形成STI区域，STI区域具有顶部宽度; 在STI区域上形成虚设电极，在硅衬底上形成栅电极，该虚拟电极的宽度大于或等于STI区域顶部宽度。

公开(公告)号：US09443871B2

公开(公告)日：2016-09-13

申请号：US14592069

申请日：2015-01-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Peter Moll ,  Jan Hoentschel

IPC: H01L29/49 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/321 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L29/417 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L27/1207 ,  H01L21/308 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7838

Abstract: A method of forming a semiconductor device structure includes providing a substrate with a semiconductor-on-insulator (SOI) configuration, the SOI substrate comprising a semiconductor layer formed on a buried oxide (BOX) layer which is disposed on a semiconductor bulk substrate, forming trench isolation structures delineating a first region and a second region within the SOI substrate, removing the semiconductor layer and the BOX layer in the first region for exposing the semiconductor bulk substrate within the first region, forming a first semiconductor device with an electrode in and over the exposed semiconductor bulk substrate in the first region, forming a second semiconductor device in the second region, the second semiconductor device comprising a gate structure disposed over the semiconductor layer and the BOX layer in the second region, and performing a polishing process for defining a common height level to which the electrode and the gate structure substantially extend.

Abstract translation: 一种形成半导体器件结构的方法包括：提供具有绝缘体上半导体（SOI）结构的衬底，所述SOI衬底包括形成在半导体本体衬底上的掩埋氧化物（BOX）层上形成的半导体层，形成 描绘SOI衬底内的第一区域和第二区域的沟槽隔离结构，去除第一区域中的半导体层和BOX层，用于在第一区域内暴露半导体本体衬底，形成具有电极的第一半导体器件 在所述第一区域中暴露的半导体体基板，在所述第二区域中形成第二半导体器件，所述第二半导体器件包括设置在所述半导体层上的栅极结构和所述第二区域中的BOX层，以及执行用于定义 电极和栅极结构基本上延伸的公共高度电平。

公开(公告)号：US20160118483A1

公开(公告)日：2016-04-28

申请号：US14522000

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66818 ,  H01L25/0657 ,  H01L29/0634 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material.

Abstract translation: 本公开在本公开的各个方面提供一种半导体器件，其包括设置在衬底的表面上的半导体堆叠和部分地形成在半导体堆叠的上表面和两个相对的侧壁表面上的栅极结构，其中， 半导体堆叠包括由第一半导体材料和与第一半导体材料不同的第二半导体材料形成的至少两层的交替布置。

公开(公告)号：US09324869B1

公开(公告)日：2016-04-26

申请号：US14613425

申请日：2015-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Jan Hoentschel

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L21/306 ,  H01L29/10 ,  H01L21/762 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L21/30608 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

Abstract: The present disclosure provides, in various aspects, a method of forming a semiconductor device and accordingly formed semiconductor devices. In accordance with some illustrative embodiments herein, a fin is provided in an upper surface of a substrate, the fin having a height dimension and an initial width dimension. After forming a mask on the fin, wherein the mask only partially covers an upper surface of the fin, the fin is exposed to an etch process for removing material in accordance with the mask such that a channel portion connecting end portions of the fin is formed. Herein, a width dimension of the channel portion is smaller than a width dimension of the end portions. In accordance with some illustrative embodiments of the present disclosure, the channel portion may substantially have a cross-section of one of a triangular shape and a double-sigma shape.

Abstract translation: 本公开在各个方面提供了一种形成半导体器件并相应地形成的半导体器件的方法。 根据这里的一些说明性实施例，在衬底的上表面中设置翅片，翅片具有高度尺寸和初始宽度尺寸。 在翅片上形成掩模之后，其中掩模仅部分地覆盖翅片的上表面，翅片暴露于根据掩模去除材料的蚀刻工艺，使得形成连接翅片的端部的通道部分 。 这里，通道部分的宽度尺寸小于端部的宽度尺寸。 根据本公开的一些示例性实施例，通道部分可以基本上具有三角形形状和双西格玛形状之一的横截面。

公开(公告)号：US20160064515A1

公开(公告)日：2016-03-03

申请号：US14471660

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gerd Zschatzsch ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/66 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76885 ,  H01L23/485 ,  H01L29/517 ,  H01L29/66606 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One exemplary embodiment provides a method of making an integrated circuit. The method includes forming a dummy gate structure above a semiconductor substrate, etching an exposed semiconductor substrate outside the dummy gate structure, depositing silicon oxide over the dummy gate structure and the semiconductor substrate to form a silicon oxide layer, etching source and drain contact vias through the silicon oxide layer, implanting source and drain dopants through the source and drain contact vias, removing the dummy gate structure, forming a final gate structure, etching substantially all of the silicon oxide layer, and depositing an ultra low K dielectric to form an ultra low K dielectric layer.

Abstract translation: 一个示例性实施例提供了制造集成电路的方法。 该方法包括在半导体衬底之上形成虚拟栅极结构，蚀刻在虚拟栅极结构之外的暴露的半导体衬底，在虚拟栅极结构和半导体衬底上沉积氧化硅以形成氧化硅层，蚀刻源极和漏极接触通孔 氧化硅层，通过源极和漏极接触通孔注入源极和漏极掺杂剂，去除虚拟栅极结构，形成最终的栅极结构，蚀刻基本上所有的氧化硅层，以及沉积超低K电介质以形成超 低K电介质层。

公开(公告)号：US09214396B1

公开(公告)日：2015-12-15

申请号：US14294467

申请日：2014-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Gerd Zschaetzsch

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/45 ,  H01L21/285 ,  H01L21/265

CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/823412 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.

Abstract translation: 提供了一种形成晶体管器件的方法，包括随后执行的步骤，在第一半导体层上形成栅电极，在栅电极和第一半导体层上形成层间电介质，在层间电介质中形成第一开口 在栅电极的一侧上与栅电极横向间隔开的预定距离，并且在栅极电极的另一侧与栅电极横向间隔开预定距离的层间电介质中的第二开口，第一和第二开口到达第一 半导体层，通过形成在层间电介质中的第一和第二开口在第一半导体层中形成空腔，以及在空腔中形成嵌入的第二半导体层。

公开(公告)号：US20150340380A1

公开(公告)日：2015-11-26

申请号：US14817734

申请日：2015-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Matthias Kessler ,  Jan Hoentschel

IPC: H01L27/12 ,  H01L29/94 ,  H01L29/06 ,  H01L29/778 ,  H01L29/16 ,  H01L29/20 ,  H01L29/861 ,  H01L29/78

CPC classification number: H01L21/84 ,  H01L21/02428 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66181 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/861 ,  H01L29/945

Abstract: A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

Abstract translation: 一种结构包括半导体衬底，绝缘体上半导体区域和体区域。 绝缘体上半导体区域包括第一半导体区域，设置在半导体衬底和第一半导体区域之间的电介质层，以及包括设置在第一半导体区域中的有源区的第一晶体管。 电介质层在第一半导体区域和半导体衬底之间提供电隔离。 本体区域包括直接设置在半导体衬底上的第二半导体区域。

公开(公告)号：US20150333057A1

公开(公告)日：2015-11-19

申请号：US14276515

申请日：2014-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Andreas Kurz ,  Sven Beyer ,  Wolfgang Buchholtz

IPC: H01L27/07 ,  H01L49/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/20 ,  H01L29/66545

Abstract: The present disclosure relates to a semiconductor structure comprising a resistor, at least part of the resistor forming a meandering shape in a vertical direction with respect to a substrate of the semiconductor structure. The disclosure further relates to a semiconductor manufacturing process comprising a step for realizing at least one first fin, and a step for realizing a resistor comprising a meandering shape in a vertical direction based on the at least one first fin.

Abstract translation: 本公开涉及包括电阻器的半导体结构，所述电阻器的至少一部分相对于半导体结构的衬底在垂直方向上形成曲折形状。 本发明还涉及包括用于实现至少一个第一鳍的步骤的半导体制造工艺，以及基于至少一个第一鳍实现在垂直方向上包括曲折形状的电阻的步骤。

公开(公告)号：US09177803B2

公开(公告)日：2015-11-03

申请号：US14175288

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/0883 ,  H01L21/26586 ,  H01L21/28 ,  H01L21/28255 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651

Abstract: The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel.

Abstract translation: 本公开提供半导体器件结构，其具有设置在半导体衬底内的第一PMOS有源区和第二PMOS有源区。 硅锗沟道层仅形成在第二PMOS有源区上。 栅电极形成在第一和第二PMOS有源区上，其中第二PMOS有源区上的栅电极形成在硅锗通道上。