公开(公告)号：US20180374951A1

公开(公告)日：2018-12-27

申请号：US15777707

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  JACOB M. JENSEN ,  DANIEL B. AUBERTINE ,  CHANDRA S. MOHAPATRA

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Tensile strain is applied to a channel region of a transistor by depositing an amorphous SixGe1-x-yCy alloy in at least one of a source and a drain (S/D) region of the transistors. The amorphous SixGe1-x-yCy alloy is crystallized, thus reducing the unit volume of the alloy. This volume reduction in at least one of the source and the drain region applies strain to a connected channel region. This strain improves electron mobility in the channel. Dopant activation in the source and drain locations is recovered during conversion from amorphous to crystalline structure. Presence of high carbon concentrations reduces dopant diffusion from the source and drain locations into the channel region. The techniques may be employed with respect to both planar and non-planar (e.g., FinFET and nanowire) transistors.

公开(公告)号：US20180342582A1

公开(公告)日：2018-11-29

申请号：US16037728

申请日：2018-07-17

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/778 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/423 ,  H01L29/417 ,  H01L29/36 ,  H01L29/167 ,  H01L29/165 ,  H01L29/08 ,  H01L27/092 ,  H01L23/535 ,  H01L21/768 ,  H01L21/3215 ,  H01L21/285

Abstract: Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

公开(公告)号：US20180337183A1

公开(公告)日：2018-11-22

申请号：US16050590

申请日：2018-07-31

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  Anand S. MURTHY

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/8238 ,  H01L21/308

CPC classification number: H01L27/0924 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.

公开(公告)号：US20180331184A1

公开(公告)日：2018-11-15

申请号：US15777553

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  KARTHIK JAMBUNATHAN ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  SEIYON KIM ,  JUN SUNG KANG

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/78 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Techniques are disclosed for fabricating semiconductor transistor devices configured with a sub-fin insulation layer that reduces parasitic leakage (i.e., current leakage through a portion of an underlying substrate between a source region and a drain region associated with a transistor). The parasitic leakage is reduced by fabricating transistors with a sacrificial layer in a sub-fin region of the substrate below at least a channel region of the fin. During processing, the sacrificial layer in the sub-fin region is removed and replaced, either in whole or in part, with a dielectric material. The dielectric material increases the electrical resistivity of the substrate between corresponding source and drain portions of the fin, thus reducing parasitic leakage.

公开(公告)号：US20180240874A1

公开(公告)日：2018-08-23

申请号：US15754150

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： CORY E. WEBER ,  SAURABH MORARKA ,  RITESH JHAVERI ,  GLENN A. GLASS ,  SZUYA S. LIAO ,  ANAND S. MURTHY

IPC: H01L29/08 ,  H01L21/225 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L21/2252 ,  H01L21/30612 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for resistance reduction under transistor spacers. In some instances, the techniques include reducing the exposure of source/drain (S/D) dopants to thermal cycles, thereby reducing the diffusion and loss of S/D dopants to surrounding materials. In some such instances, the techniques include delaying the epitaxial deposition of the doped S/D material until near the end of the transistor formation process flow, thereby avoiding the thermal cycles earlier in the process flow. For example, the techniques may include replacing the S/D regions (e.g., native fin material in the regions to be used for the transistor S/D) with sacrificial S/D material that can then be selectively etched and replaced by highly doped epitaxial S/D material later in the process flow. In some cases, the selective etch may be performed through S/D contact trenches formed in overlying insulator material over the sacrificial S/D.

公开(公告)号：US20170358645A1

公开(公告)日：2017-12-14

申请号：US15525269

申请日：2014-12-26

Applicant: INTEL CORPORATION

Inventor： GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  TAHIR GHANI ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  SANAZ K. GARDNER ,  MARKO RADOSAVLJEVIC ,  GLENN A. GLASS

IPC: H01L29/06 ,  H01L29/12 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L29/775 ,  H01L21/306 ,  H01L21/02 ,  H01L29/20 ,  H01L29/161 ,  H01L29/04

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/7605 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/122 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.

公开(公告)号：US20170323962A1

公开(公告)日：2017-11-09

申请号：US15525164

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  TAHIR GHANI ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  HAROLD W. KENNEL ,  GLENN A. GLASS

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7781

Abstract: An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least one of a group III-V material and a group IV material; a fin structure, directly over the trench, including fin material having: (b) (ii) a second bulk lattice constant and (b)(ii) at least one of a group III-V material and a group IV material; a barrier layer, within the trench and directly contacting a bottom surface of the fin, including a barrier layer material having a third bulk lattice constant; wherein (a) the trench has an aspect ratio (depth to width) of at least 1.5:1, and (b) the barrier layer has a height not greater than a critical thickness for the barrier layer material. Other embodiments are described herein.

公开(公告)号：US20170221724A1

公开(公告)日：2017-08-03

申请号：US15489569

申请日：2017-04-17

Applicant: INTEL CORPORATION

Inventor： ANAND S. MURTHY ,  GLENN A. GLASS ,  TAHIR GHANI ,  RAVI PILLARISETTY ,  NILOY MUKHERJEE ,  JACK T. KAVALIEROS ,  ROZA KOTLYAR ,  WILLY RACHMADY ,  MARK Y. LIU

IPC: H01L21/3215 ,  H01L29/06 ,  H01L29/778 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

公开(公告)号：US20170162447A1

公开(公告)日：2017-06-08

申请号：US15125437

申请日：2014-06-24

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN

IPC: H01L21/8238 ,  H01L29/10 ,  H01L29/165 ,  H01L29/205 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/823821 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.

公开(公告)号：US20170040438A1

公开(公告)日：2017-02-09

申请号：US15295938

申请日：2016-10-17

Applicant: INTEL CORPORATION

Inventor： ANNALISA CAPPELLANI ,  VAN H. LE ,  GLENN A. GLASS ,  KELIN J. KUHN ,  STEPHEN M. CEA

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/76 ,  H01L21/7624 ,  H01L21/76283 ,  H01L29/0603 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/7378 ,  H01L29/785 ,  H01L33/12 ,  H05K1/18

Abstract: Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.

Abstract translation: 公开了用于将应变诱导半导体缓冲层转化为缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括由于生长而产生的那些 在应变诱导缓冲器上并具有埋入的电绝缘体层。 例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fin 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。 此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。 在一些实施例中，基本上整个缓冲层被转换成电绝缘体。