公开(公告)号：US09728640B2

公开(公告)日：2017-08-08

申请号：US14823344

申请日：2015-08-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Bruce B. Doris ,  Hong He ,  Rajasekhar Venigalla

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/02 ,  H01L29/04 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L27/1211 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.

公开(公告)号：US20170098665A1

公开(公告)日：2017-04-06

申请号：US15381441

申请日：2016-12-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Bruce B. Doris ,  Hong He ,  Rajasekhar Venigalla

IPC: H01L27/12 ,  H01L29/04 ,  H01L21/02 ,  H01L29/08 ,  H01L21/84 ,  H01L21/308

CPC classification number: H01L27/1211 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.

公开(公告)号：US20160336322A1

公开(公告)日：2016-11-17

申请号：US15219922

申请日：2016-07-26

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Miaomiao Wang ,  Tenko Yamashita

IPC: H01L27/092 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/033

CPC classification number: H01L27/0924 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7855

Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

Abstract translation: 提供了一种用于形成半导体器件的技术。 牺牲心轴形成在半导体层上的硬掩模层上。 垫片形成在牺牲心轴的侧壁上。 去除牺牲心轴以留下间隔物。 掩蔽过程使第一组间隔物暴露出第二组保护。 响应于掩蔽过程，第一鳍蚀刻工艺通过第一组间隔件在半导体层中形成第一组散热片。 第一组翅片具有垂直的侧壁轮廓。 另一掩蔽工艺使第二组间隔件与第一组间隔件露出，第一组散热片被保护。 响应于另一掩蔽工艺，第二鳍蚀刻工艺使用第二组间隔件在半导体层中形成第二组散热片。 第二组翅片具有梯形侧壁轮廓。

公开(公告)号：US20160336236A1

公开(公告)日：2016-11-17

申请号：US15219894

申请日：2016-07-26

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Miaomiao Wang ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L27/0924 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7855

Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

公开(公告)号：US09484431B1

公开(公告)日：2016-11-01

申请号：US14812399

申请日：2015-07-29

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L29/00 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/225 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/311 ,  H01L29/167 ,  H01L29/08

CPC classification number: H01L29/456 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

公开(公告)号：US20160247685A1

公开(公告)日：2016-08-25

申请号：US14630072

申请日：2015-02-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Miaomiao Wang ,  Tenko Yamashita

IPC: H01L21/308 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7855

Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

公开(公告)号：US20160211343A1

公开(公告)日：2016-07-21

申请号：US15068973

申请日：2016-03-14

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/49 ,  H01L29/51

CPC classification number: H01L29/49 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/285 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region. The method also includes implanting metal ions at a selected depth within the upper surface of the semiconductor region and converting the upper surface of the semiconductor region to a metal oxide insulating layer. The method further includes forming a metal layer on the insulating layer.

公开(公告)号：US20160211340A1

公开(公告)日：2016-07-21

申请号：US14600077

申请日：2015-01-20

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/45 ,  H01L29/417 ,  H01L21/321 ,  H01L21/311 ,  H01L21/265 ,  H01L21/02 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L29/49 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/285 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region. The method also includes implanting metal ions at a selected depth within the upper surface of the semiconductor region and converting the upper surface of the semiconductor region to a metal oxide insulating layer. The method further includes forming a metal layer on the insulating layer.

公开(公告)号：US09331146B2

公开(公告)日：2016-05-03

申请号：US14301587

申请日：2014-06-11

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Tenko Yamashita

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/306 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/0669 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02186 ,  H01L21/28079 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31056 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate, forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, and performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer, thereby defining a nanowire structure from the fin structure.

Abstract translation: 提供了半导体器件的技术。 技术涉及通过以下方式形成半导体器件：在衬底中形成翅片结构，在鳍结构的上部形成保护层，保护层相对于鳍结构的材料具有蚀刻选择性，并执行 底切蚀刻，以便在保护层下方去除翅片结构的下部，从而从翅片结构限定纳米线结构。

公开(公告)号：US12217158B2

公开(公告)日：2025-02-04

申请号：US16558554

申请日：2019-09-03

Applicant: International Business Machines Corporation

Inventor： Xiao Sun ,  Jungwook Choi ,  Naigang Wang ,  Chia-Yu Chen ,  Kailash Gopalakrishnan

IPC: G06N3/063 ,  G06N3/084

Abstract: An apparatus includes circuitry for a neural network that is configured to perform forward propagation neural network operations on floating point numbers having a first n-bit floating point format. The first n-bit floating point format has a configuration consisting of a sign bit, m exponent bits and p mantissa bits where m is greater than p. The circuitry is further configured to perform backward propagation neural network operations on floating point numbers having a second n-bit floating point format that is different than the first n-bit floating point format. The second n-bit floating point format has a configuration consisting of a sign bit, q exponent bits and r mantissa bits where q is greater than m and r is less than p.