公开(公告)号：US20180047783A1

公开(公告)日：2018-02-15

申请号：US15792585

申请日：2017-10-24

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L27/24 ,  G11C5/02 ,  G11C13/00 ,  G11C11/34 ,  G11C11/56 ,  H01L45/00 ,  H01L29/66

Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

公开(公告)号：US09831246B2

公开(公告)日：2017-11-28

申请号：US13925471

申请日：2013-06-24

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L27/098 ,  H01L29/808 ,  H01L27/12 ,  H01L29/80 ,  H01L29/66 ,  H01L21/322 ,  H01L21/22 ,  H01L21/225 ,  H01L21/385 ,  H01L27/108

CPC classification number: H01L27/098 ,  H01L21/22 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/3226 ,  H01L21/385 ,  H01L27/108 ,  H01L27/1203 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/80 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8086

Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

公开(公告)号：US20170317099A1

公开(公告)日：2017-11-02

申请号：US15651916

申请日：2017-07-17

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L27/1157 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US09761599B2

公开(公告)日：2017-09-12

申请号：US14827695

申请日：2015-08-17

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Chandra Mouli ,  Sergei Koveshnikov ,  Dimitrios Pavlopoulos ,  Guangyu Gavin Huang

IPC: H01L27/115 ,  H01L29/792 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

公开(公告)号：US20170069732A1

公开(公告)日：2017-03-09

申请号：US15354572

申请日：2016-11-17

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/66 ,  H01L29/88 ,  H01L29/06 ,  H01L29/872 ,  H01L29/417

CPC classification number: H01L29/66151 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/283 ,  H01L28/90 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/88 ,  H01L45/00

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Abstract translation: 一些实施例包括形成二极管的方法，其中第一电极形成为具有从基部向上延伸的基座。 沿着延伸穿过基座和基底的波状形貌沉积至少一层，并且在最少一层上形成第二电极。 第一电极，至少一层和第二电极一起形成当一个极性的电压施加到结构时在第一和第二电极之间传导电流的结构，并且当电压具有 与所述一个极性相反的极性被施加到该结构。 一些实施例包括具有第一电极的二极管，该第一电极包含从基底向上延伸的两个或更多个突起，在第一电极上具有至少一个层，并且在该至少一个层上具有第二电极。

公开(公告)号：US09537091B2

公开(公告)日：2017-01-03

申请号：US14471569

申请日：2014-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chandra Mouli ,  Roy Meade

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/06 ,  G11C13/0097 ,  H01L27/2481 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1683

Abstract: Memory cells and methods of forming the same and devices including the same. The memory cells have first and second electrodes. An amorphous semiconductor material capable of electronic switching and having a first band gap is between the first and second electrodes. A material is in contact with the semiconductor material and having a second band gap, the second band gap greater than the first band gap.

Abstract translation: 存储单元及其形成方法以及包括其的装置。 存储单元具有第一和第二电极。 能够进行电子开关并具有第一带隙的非晶半导体材料位于第一和第二电极之间。 材料与半导体材料接触并具有第二带隙，第二带隙大于第一带隙。

公开(公告)号：US09450024B2

公开(公告)日：2016-09-20

申请号：US15004744

申请日：2016-01-22

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/24 ,  H01L29/786 ,  H01L29/66 ,  H01L45/00

CPC classification number: H01L27/2454 ,  H01L21/02568 ,  H01L27/11582 ,  H01L27/2463 ,  H01L29/0603 ,  H01L29/24 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L29/7926 ,  H01L45/065 ,  H01L45/141 ,  H01L45/16

Abstract: In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers.

Abstract translation: 在一些实施例中，晶体管包括具有底部源极/漏极区域，第一绝缘材料，导电栅极，第二绝缘材料和顶部源极/漏极区域的堆叠。 该堆叠具有沿着底部源极/漏极区域具有底部的垂直侧壁，沿着导电栅极的中间部分和沿着顶部源极/漏极区域的顶部部分。 第三绝缘材料沿着垂直侧壁的中间部分。 沟道区域材料沿着第三绝缘材料。 通道区域材料直接抵靠垂直侧壁的顶部和底部。 沟道区域材料的厚度在大于约至小于或等于的范围内; 和/或具有1个单层至7个单层的厚度。

公开(公告)号：US20160225860A1

公开(公告)日：2016-08-04

申请号：US15095211

申请日：2016-04-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L29/24 ,  H01L29/10 ,  H01L29/06 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L27/11597 ,  G11C11/22 ,  H01L21/02568 ,  H01L21/28291 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L2029/42388

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

公开(公告)号：US09276092B1

公开(公告)日：2016-03-01

申请号：US14516396

申请日：2014-10-16

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/267 ,  H01L21/02

CPC classification number: H01L45/1206 ,  H01L21/02532 ,  H01L21/02568 ,  H01L23/535 ,  H01L27/115 ,  H01L27/228 ,  H01L27/2454 ,  H01L29/12 ,  H01L29/267 ,  H01L29/66666 ,  H01L29/66969 ,  H01L29/66977 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L43/02 ,  H01L43/10 ,  H01L45/142 ,  H01L45/143

Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

Abstract translation: 一些实施例包括具有漏极区域和源极区域的晶体管。 导电栅极位于源区和漏区之间。 第一通道材料位于栅极和源极区域之间。 第一通道材料通过一种或多种绝缘材料与栅极间隔开。 第二通道材料位于第一通道材料和源极区之间，并直接接触源区。 第一和第二通道材料是过渡金属硫族化物。 源区和漏区中的一个是孔储存区，另一个是电子储存区。 隧道介电材料可以在第一和第二通道材料之间。

公开(公告)号：US09076686B1

公开(公告)日：2015-07-07

申请号：US14152664

申请日：2014-01-10

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/66 ,  H01L29/06 ,  H01L29/24 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/0603 ,  H01L29/24 ,  H01L29/66666

Abstract: A field effect transistor construction comprises two source/drain regions and a channel region there-between. The channel region comprises a transition metal dichalcogenide material having a thickness of 1 monolayer to 7 monolayers and having a physical length between the source/drain regions. A mid-gate is operatively proximate a mid-portion of the channel region relative to the physical length. A pair of gates is operatively proximate different respective portions of the channel region from the portion of the channel region that the mid-gate is proximate. The pair of gates are spaced and electrically isolated from the mid-gate on opposite sides of the mid-gate. Gate dielectric is between a) the channel region, and b) the mid-gate and the pair of gates. Additional embodiments are disclosed.

Abstract translation: 场效应晶体管结构包括两个源极/漏极区域和其间的沟道区域。 通道区域包含厚度为1单层至7层的过渡金属二硫属元素材料，并且在源极/漏极区域之间具有物理长度。 中间栅极相对于物理长度可操作地邻近沟道区的中部。 一对门可操作地接近沟道区域与中栅极接近的沟道区域的部分的不同相应部分。 一对门与中门对面的中间门隔开并与之隔离。 栅极电介质位于a）沟道区域之间，b）中间栅极与栅极对之间。 公开了另外的实施例。