中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

60 records (took 0.061 seconds)

    Method, interconnect and system for testing semiconductor components
    31.
    发明申请
    Method, interconnect and system for testing semiconductor components 有权
    用于测试半导体元件的方法，互连和系统

    公开(公告)号：US20060181298A1

    公开(公告)日：2006-08-17

    申请号：US11057500

    申请日：2005-02-14

    Applicant: Warren Farnworth ,  Mark Tuttle

    Inventor： Warren Farnworth ,  Mark Tuttle

    IPC: G01R31/26

    CPC classification number: G01R31/2886

    Abstract: A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. A system includes the interconnect, an alignment system for aligning the substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation.

    Abstract translation: 用于测试半导体部件的方法包括以下步骤：将互连件连接到部件以形成结合的电连接，通过结合的电连接施加测试信号，然后将该互连件与部件分离。 接合步骤可以使用冶金结合进行，并且分离步骤可以使用在互连或部件上的可焊接润湿和焊接不可润湿的金属层进行。 在分离步骤期间，可焊接润湿层被溶解，减少了粘合的电连接的粘合性，并允许部件和互连的分离。 互连包括被配置用于结合到组件上并且然后与组件上的组件触点分离的互连触点。 系统包括互连，用于将衬底对准互连的对准系统，用于将组件粘合到互连的接合系统，以及用于加热组件和用于分离的互连的加热系统。

    Integrated circuits with contemporaneously formed array electrodes and logic interconnects
    33.
    发明申请
    Integrated circuits with contemporaneously formed array electrodes and logic interconnects 审中-公开
    具有同时形成的阵列电极和逻辑互连的集成电路

    公开(公告)号：US20060099797A1

    公开(公告)日：2006-05-11

    申请号：US11315731

    申请日：2005-12-22

    Applicant: Mirmajid Seyyedy ,  Glen Hush ,  Mark Tuttle ,  Terry Vollman

    Inventor： Mirmajid Seyyedy ,  Glen Hush ,  Mark Tuttle ,  Terry Vollman

    IPC: H01L21/4763 ,  H01L21/336 ,  H01L21/8242

    CPC classification number: H01L27/228 ,  G11C5/06 ,  G11C11/14 ,  H01L27/105 ,  H01L27/10882 ,  H01L27/10897

    Abstract: The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention further include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting simultaneous fabrication of array electrodes and electrical interconnects in different areas of the chip. This reduces the number of fabrication steps used to make interconnects, thereby speeding up fabrication and reducing production costs.

    Abstract translation: 本发明涉及用于集成电路存储器件的互连。 本发明的实施例包括以相对较少的步骤制造用于存储器件的互连的工艺。 本发明的实施例还包括具有在芯片的不同区域中具有不等间距尺寸的金属化层的存储器件，从而允许在芯片的不同区域中同时制造阵列电极和电互连。 这减少了用于制造互连的制造步骤的数量，从而加快制造并降低生产成本。

    Electronic Communication Devices, Methods Of Forming Electrical Communication Devices, And Communications Methods
    40.
    发明申请
    Electronic Communication Devices, Methods Of Forming Electrical Communication Devices, And Communications Methods 有权
    电子通信设备，形成电气通信设备的方法和通信方法

    公开(公告)号：US20070290862A1

    公开(公告)日：2007-12-20

    申请号：US11846905

    申请日：2007-08-29

    Applicant: Mark Tuttle

    Inventor： Mark Tuttle

    IPC: G08B13/14

    CPC classification number: G06K7/0008 ,  G06K19/07749 ,  G06K19/07771 ,  G06K19/07786

    Abstract: The present invention provides electronic communication devices, methods of forming electrical communication devices, and communications methods. An electronic communication device adapted to receive electronic signals includes: a housing comprising a substrate and an encapsulant; an integrated circuit provided within the housing and comprising transponder circuitry operable to communicate an identification signal responsive to receiving a polling signal; an antenna provided within the housing and being coupled with the transponder circuitry; and a ground plane provided within the housing and being spaced from the antenna and configured to shield some of the electronic signals from the antenna and reflect others of the electronic signals towards the antenna. A method of forming an electronic signal communication device includes providing a substrate having a support surface; providing a conductive layer adjacent at least a portion of the support surface; providing a dielectric layer over the conductive layer; providing an antenna over the dielectric layer; coupling an integrated circuit with the antenna; and encapsulating the antenna, the dielectric layer, and the integrated circuit using a flowable encapsulant.

    Abstract translation: 本发明提供电子通信设备，形成电通信设备的方法和通信方法。 适于接收电子信号的电子通信设备包括：壳体，包括衬底和密封剂; 设置在所述外壳内的集成电路，包括响应于接收到轮询信号而传送识别信号的应答器电路; 设置在壳体内并与应答器电路耦合的天线; 以及设置在壳体内并与天线间隔开并被配置为将一些电子信号与天线隔离并将其它电子信号反射向天线的接地平面。 一种形成电子信号通信装置的方法包括提供具有支撑表面的基板; 提供邻近所述支撑表面的至少一部分的导电层; 在所述导电层上提供介电层; 在电介质层上提供天线; 将集成电路与天线耦合; 并使用可流动的密封剂封装天线，电介质层和集成电路。

Patent Agency Ranking