公开(公告)号：US09837209B2

公开(公告)日：2017-12-05

申请号：US13684072

申请日：2012-11-21

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young K. Song ,  Changhan Yun ,  Dong Wook Kim

IPC: H01G4/00 ,  H01G4/30 ,  H01G4/005 ,  H01G4/232 ,  H01G4/224 ,  H01G4/002 ,  H01G4/012 ,  H01G4/33 ,  H01L23/50

CPC classification number: H01G4/002 ,  H01G4/012 ,  H01G4/33 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/19105 ,  Y10T29/417 ,  H01L2924/00

Abstract: Some novel features pertain to a capacitor structure that includes a first conductive layer, a second conductive layer and a non-conductive layer. The first conductive layer has a first overlapping portion and a second overlapping portion. The second conductive layer has a third overlapping portion, a fourth overlapping portion, and a non-overlapping portion. The third overlapping portion overlaps with the first overlapping portion of the first conductive layer. The fourth overlapping portion overlaps with the second overlapping portion of the first conductive layer. The non-overlapping portion is free of any overlap (e.g., vertical overlap) with the first conductive layer. The non-conductive layer separates the first and second conductive layers. The non-conductive layer electrically insulates the third overlapping portion and the fourth overlapping portion from the first conductive layer.

公开(公告)号：US09472425B2

公开(公告)日：2016-10-18

申请号：US14663342

申请日：2015-03-19

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Jae Sik Lee

IPC: H01L21/48 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L21/4846 ,  H01G4/33 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/3192 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/642 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L28/60 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/16238 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/185 ,  H05K3/4661

Abstract: A fan-out wafer level package structure may include a multilayer redistribution layer (RDL). The multilayer RDL may be configured to couple with terminals of an embedded capacitor. The multilayer RDL may include sections with fewer layers than other sections of the multilayer RDL according to a selected equivalent series resistance (ESR) control pattern.

Abstract translation: 扇出晶片级封装结构可以包括多层再分配层（RDL）。 多层RDL可以被配置为与嵌入式电容器的端子耦合。 根据所选择的等效串联电阻（ESR）控制模式，多层RDL可以包括具有比多层RDL的其它部分更少的层的部分。

公开(公告)号：US20160183379A1

公开(公告)日：2016-06-23

申请号：US14579735

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Kyu-Pyung Hwang

IPC: H05K1/18 ,  H05K3/32

CPC classification number: H05K1/185 ,  H01G4/224 ,  H01G4/232 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K2201/10015 ,  H05K2203/1469

Abstract: A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a base portion, a first terminal and a second terminal. The first terminal is located on a first surface of the base portion, where the first terminal is the only terminal on the first surface of the base portion. The second terminal is located on a second surface of the base portion. The second surface is opposite to the first surface. The second terminal is the only terminal on the second surface of the base portion. In some implementations, the capacitor further includes a first base metal layer located between the first surface of the base portion and the first terminal. In some implementations, the capacitor also includes a second base metal layer located between the second surface of the base portion and the second terminal.

Abstract translation: 一种衬底，其包括第一介电层和嵌入第一介电层中的电容器。 电容器包括基部，第一端子和第二端子。 第一端子位于基部的第一表面上，其中第一端子是基部的第一表面上的唯一端子。 第二端子位于基部的第二表面上。 第二表面与第一表面相对。 第二端子是基部的第二表面上的唯一端子。 在一些实施方式中，电容器还包括位于基部的第一表面和第一端之间的第一基底金属层。 在一些实施方式中，电容器还包括位于基部的第二表面和第二端之间的第二基底金属层。

公开(公告)号：US20160183378A1

公开(公告)日：2016-06-23

申请号：US14579651

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/46 ,  H01G4/012 ,  H05K3/40 ,  H01G4/30 ,  H01G4/248 ,  H05K1/11 ,  H05K3/30

CPC classification number: H05K1/185 ,  H01G4/005 ,  H01G4/012 ,  H01G4/232 ,  H01G4/248 ,  H01G4/30 ,  H01L23/50 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K3/30 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/46 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0187 ,  H05K2201/09781 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a first terminal, a second terminal, and a third terminal. The second terminal is laterally located between the first terminal and the third terminal. The capacitor also includes a second dielectric layer, a first metal layer and a second metal layer. The first metal layer is coupled to the first and third terminals. The first metal layer, the first terminal, and the third terminal are configured to provide a first electrical path for a first signal. The second metal layer is coupled to the second terminal. The second metal layer and the second terminal are configured to provide a second electrical path for a second signal.

Abstract translation: 一种衬底，其包括第一介电层和嵌入第一介电层中的电容器。 电容器包括第一端子，第二端子和第三端子。 第二端子横向位于第一端子和第三端子之间。 电容器还包括第二电介质层，第一金属层和第二金属层。 第一金属层耦合到第一和第三端子。 第一金属层，第一端子和第三端子被配置成为第一信号提供第一电路径。 第二金属层耦合到第二端子。 第二金属层和第二端子被配置成为第二信号提供第二电路径。

公开(公告)号：US20160163628A1

公开(公告)日：2016-06-09

申请号：US14563854

申请日：2014-12-08

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H05K1/16

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/4824 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/66 ,  H01L24/83 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/162 ,  H01L2924/00

Abstract: A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion includes a first dielectric layer, a first set of metal layers in the dielectric layer, a first via in the dielectric layer, a second set of metal layers in the dielectric layer, and a second via in the dielectric layer. The first via is coupled to the first set of metal layers. The first via and the first set of metal layers are configured to provide a first electrical path for a ground signal. The second via is coupled to the second set of metal layers. The second via and the second set of metal layers are configured to provide a second electrical path for a power signal. The redistribution portion includes a second dielectric layer, and a set of interconnects.

Abstract translation: 一种封装基板，包括第一部分和再分配部分。 第一部分被配置为作为电容器工作。 第一部分包括第一电介质层，电介质层中的第一组金属层，电介质层中的第一通孔，介电层中的第二组金属层和介电层中的第二通孔。 第一通孔耦合到第一组金属层。 第一通孔和第一组金属层被配置成为接地信号提供第一电路径。 第二通孔耦合到第二组金属层。 第二通孔和第二组金属层被配置成为功率信号提供第二电路径。 再分配部分包括第二介电层和一组互连。

公开(公告)号：US09294064B2

公开(公告)日：2016-03-22

申请号：US13835211

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Changhan Hobie Yun ,  Dong Wook Kim

IPC: H03H7/01 ,  H03H7/12 ,  H05K1/16 ,  H01G4/40 ,  H03H3/00

CPC classification number: H03H7/0115 ,  H01G4/40 ,  H03H3/00 ,  H03H7/12 ,  H05K1/162 ,  H05K2201/09236 ,  Y10T29/43 ,  Y10T29/49016

Abstract: A planar capacitor includes, in part, a first metal line forming spiral-shaped loops around one of its end point, and a second metal line forming spiral-shaped loops between the loops of the first metal line. The first and second metal lines are coplanar, formed on an insulating layer, and form the first and second plates of the planar capacitor. The planar capacitor may be used to form a filter. Such a filter includes a first metal line forming first spiral-shaped loops, a second metal line forming second spiral-shaped loops, and a third metal line—coplanar with the first and second metal lines—forming loops between the loops of the first and second metal lines. The filter further includes a first inductor coupled between the first and third metal lines, and a second inductor coupled between the second and third metal lines.

Abstract translation: 平面电容器部分地包括围绕其端点之一形成螺旋形环的第一金属线和在第一金属线的环之间形成螺旋形环的第二金属线。 第一和第二金属线是共面的，形成在绝缘层上，并形成平面电容器的第一和第二板。 平面电容器可以用于形成滤波器。 这种过滤器包括形成第一螺旋形环的第一金属线，形成第二螺旋状环的第二金属线和与第一和第二金属线形成环之间的第一和第二金属线形成环的第三金属线 - 共面， 第二条金属线 滤波器还包括耦合在第一和第三金属线之间的第一电感器和耦合在第二和第三金属线之间的第二电感器。

公开(公告)号：US09269610B2

公开(公告)日：2016-02-23

申请号：US14253798

申请日：2014-04-15

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Chin-Kwan Kim ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/768 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract translation: 公开了一种集成电路（IC）基板，其包括形成在第一图案化金属层之间的第二图案化金属层。 形成在第一图案化金属层上的电介质层分离两个金属层。 在介电层和第二图案化金属层上形成非导电层。

公开(公告)号：US20150340425A1

公开(公告)日：2015-11-26

申请号：US14283980

申请日：2014-05-21

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01L49/02 ,  H05K1/18 ,  H05K3/46 ,  H01L23/498

CPC classification number: H01L28/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4602 ,  H01L2924/014

Abstract: A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.

Abstract translation: 提供一种封装基板，其包括芯基板和嵌入在包括第一侧的芯基板中的电容器。 电容器包括设置在电容器的相对端的第一电极和第二电极。 封装还包括在芯基板中横向延伸的第一电源金属板。 第一电源金属板从芯基板的第一侧直接设置在电容器的第一电极上。 第一通孔，其垂直于第一金属板延伸并从芯基板的第一侧连接到第一电源金属板。

公开(公告)号：US20150294933A1

公开(公告)日：2015-10-15

申请号：US14253798

申请日：2014-04-15

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Chin-Kwan Kim ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/768 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract translation: 公开了一种集成电路（IC）基板，其包括形成在第一图案化金属层之间的第二图案化金属层。 形成在第一图案化金属层上的电介质层分离两个金属层。 在介电层和第二图案化金属层上形成非导电层。

公开(公告)号：US20150236681A1

公开(公告)日：2015-08-20

申请号：US14249189

申请日：2014-04-09

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H03K3/013 ,  H05K3/30 ,  H05K3/46 ,  G05F3/08 ,  H05K1/18 ,  H05K1/03

CPC classification number: H03K3/013 ,  G05F3/08 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/183 ,  H05K1/184 ,  H05K3/306 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/49139 ,  H01L2924/00

Abstract: An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network.

Abstract translation: 嵌入在衬底空腔中的嵌入式多端子电容器包括图案化成多个电源轨道和多个接地轨道的至少一个金属层。 基板包括外部电力网络。