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    NONVOLATILE MEMORY DEVICE WITH ON-DIE CONTROL AND DATA SIGNAL TERMINATION
    33.
    发明申请
    NONVOLATILE MEMORY DEVICE WITH ON-DIE CONTROL AND DATA SIGNAL TERMINATION 有权
    具有接通控制和数据信号终止的非易失性存储器件

    公开(公告)号：US20150229306A1

    公开(公告)日：2015-08-13

    申请号：US14695260

    申请日：2015-04-24

    Applicant: Rambus Inc.

    Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

    IPC: H03K19/00 ,  G11C16/26 ,  G11C11/419 ,  H03K19/0175 ,  G11C11/4093

    CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

    Abstract: In a non-volatile memory device having an array of non-volatile storage elements, control information received via one or more control input nodes indicates, at different times, that (i) data signals representative of data to be stored within the array of non-volatile storage elements are to be received via a plurality of input/output (I/O) nodes of the non-volatile memory device, and (ii) data signals representative of data read from the array of non-volatile storage elements are to be output via the plurality of I/O nodes. First termination elements are switchably coupled to and decoupled from the I/O nodes based at least in part on the control information, and second termination elements are switchably coupled to and decoupled from the one or more control input nodes based at least in part on the control information.

    Abstract translation: 在具有非易失性存储元件的阵列的非易失性存储器件中，经由一个或多个控制输入节点接收的控制信息在不同时间指示（i）表示要存储在非阵列阵列内的数据的数据信号， 非挥发性存储元件将通过非易失性存储器件的多个输入/输出（I / O）节点接收，并且（ii）代表从非易失性存储元件阵列读取的数据的数据信号是 通过多个I / O节点输出。 至少部分地基于控制信息，第一终端元件可切换地耦合到I / O节点并从I / O节点去耦，并且第二终端元件至少部分地基于控制信息而切换地耦合到一个或多个控制输入节点并从该一个或多个控制输入节点去耦 控制信息。

    Memory disturbance recovery mechanism
    34.
    发明授权
    Memory disturbance recovery mechanism 有权
    记忆障碍恢复机制

    公开(公告)号：US09104646B2

    公开(公告)日：2015-08-11

    申请号：US14098322

    申请日：2013-12-05

    Applicant: Rambus Inc.

    Inventor： Hongzhong Zheng ,  Brent Haukness ,  Mehmet Günhan Ertosun ,  Ian P. Shaeffer

    IPC: G11C11/00 ,  G06F11/20

    CPC classification number: G06F11/2053 ,  G11C13/0002 ,  G11C13/0033 ,  G11C16/3431 ,  G11C29/50008 ,  G11C29/52 ,  G11C2029/0409

    Abstract: Components of a memory system, such as a memory controller and memory device, which detect accumulated memory read disturbances and correct such disturbances before they reach a level that causes errors. The memory device includes a memory array and a disturbance control circuit. The memory array includes a plurality of memory rows. Each memory row is associated with a disturbance warning circuit having a state that corresponds to an accumulated disturbance in the memory row. The disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether the disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row. If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row to reduce the accumulated disturbances.

    Abstract translation: 诸如存储器控制器和存储器件的存储器系统的组件，其在累积的存储器读出干扰之前检测累积的存储器读取干扰并且在达到导致错误的电平之前校正这种干扰。 存储器件包括存储器阵列和干扰控制电路。 存储器阵列包括多个存储器行。 每个存储器行与具有对应于存储器行中的累积干扰的状态的干扰警告电路相关联。 干扰控制电路响应于由行访问命令指定的多个存储行的存储器行的激活，基于与存储器相关联的干扰警告电路的状态来确定存储器行中是否存在干扰条件 行。 如果存在干扰条件，则扰动控制电路使得对存储器行进行恢复操作以减少累积的干扰。

    Reducing Memory Refresh Exit Time
    35.
    发明申请
    Reducing Memory Refresh Exit Time 有权
    减少内存刷新退出时间

    公开(公告)号：US20140016423A1

    公开(公告)日：2014-01-16

    申请号：US13938130

    申请日：2013-07-09

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent Haukness ,  Ian P. Shaeffer ,  James E. Harris

    IPC: G11C7/00

    CPC classification number: G11C7/00 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40622

    Abstract: Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal.

    Abstract translation: 诸如存储器控制器和存储器设备的存储器系统的组件通过控制存储器件的刷新定时来减少退出自刷新模式的延迟。 存储器件包括存储器核。 存储装置的接口电路接收指示间歇刷新事件的外部刷新信号。 存储器件的刷新电路产生指示存储器件的内部刷新事件的内部刷新信号。 存储器件的刷新控制电路响应于内部刷新事件，在相对于由外部刷新信号指示的间歇刷新事件的时间，对存储器核心的一部分执行刷新操作。

    Clock generation for timing communications with ranks of memory devices
    40.
    发明授权
    Clock generation for timing communications with ranks of memory devices 有权

    公开(公告)号：US11630788B2

    公开(公告)日：2023-04-18

    申请号：US16921061

    申请日：2020-07-06

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

    IPC: G06F13/16 ,  G11C7/22 ,  G06F1/10 ,  G06F1/06 ,  G06F1/08 ,  G06F1/04 ,  G11C7/04 ,  H04L7/033

    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

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