公开(公告)号：US10818650B2

公开(公告)日：2020-10-27

申请号：US16598858

申请日：2019-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: H01L25/16 ,  H01L31/105 ,  H01L31/02 ,  H01L31/0232 ,  H01L23/373 ,  H01L23/00 ,  G02B6/42 ,  H04B10/40

Abstract: The semiconductor module includes a semiconductor chip and a semiconductor chip. The semiconductor chip includes an optical device such as an optical waveguide, an optical receiver, and a grating coupler, and a wiring formed over the optical device. The semiconductor chip includes a semiconductor element such as a MISFET formed in the semiconductor substrate, and a wiring formed over the semiconductor element. a top surface of the semiconductor chip is laminated to a top surface of the semiconductor chip such that the wirings are in direct contact with each other. In the semiconductor substrate, a through hole having a circular shape in plan view is formed, in the through hole, an insulating film is formed as a cladding layer, and the semiconductor substrate surrounded by the through hole constitutes an optical waveguide.

公开(公告)号：US10527872B2

公开(公告)日：2020-01-07

申请号：US15798780

申请日：2017-10-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroyuki Kunishima ,  Yasutaka Nakashiba ,  Masaru Wakabayashi ,  Shinichi Watanuki

IPC: G02B6/26 ,  G02F1/025 ,  H01L23/532 ,  G02B6/125 ,  G02B6/132 ,  G02B6/28 ,  G02B6/12

Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.

公开(公告)号：US10416481B2

公开(公告)日：2019-09-17

申请号：US16182259

申请日：2018-11-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tohru Kawai ,  Shinichi Watanuki ,  Yasutaka Nakashiba

IPC: G02F1/025

Abstract: The performances of a semiconductor device are improved. The semiconductor device includes an insulation layer, an optical waveguide part formed over the insulation layer, and including a p type semiconductor region and an n type semiconductor region formed therein, and an interlayer insulation film formed over the insulation layer in such a manner as to cover the optical waveguide part. At the first portion of the optical waveguide part, in a cross sectional view perpendicular to the direction of extension of the optical waveguide part, the n type semiconductor region is arranged at the central part of the optical waveguide part, and the p type semiconductor region is arranged in such a manner as to surround the entire circumference of the n type semiconductor region.

公开(公告)号：US10416382B2

公开(公告)日：2019-09-17

申请号：US16176327

申请日：2018-10-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba ,  Shinichi Watanuki

IPC: G02B6/10 ,  G02B6/122 ,  G02B6/12

Abstract: In an optical waveguide section of an SIS type having a configuration of stacking a second semiconductor layer over a first semiconductor layer with a dielectric layer interposed, the first semiconductor layer is electrically coupled to a first electrode at a first lead-out section where the second semiconductor layer is not stacked. Further, the second semiconductor layer is electrically coupled to a second electrode at a second lead-out section not overlapping with the first semiconductor layer. As a result, when a contact hole for forming the second electrode is formed by dry etching, the dielectric layer between the first semiconductor layer and the second semiconductor layer is not damaged or broken and hence short-circuit failure between the first semiconductor layer and the second semiconductor layer can be prevented. The reliability of the optical waveguide section therefore can be improved.

公开(公告)号：US10197822B2

公开(公告)日：2019-02-05

申请号：US15878619

申请日：2018-01-24

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Kuwabara ,  Yasutaka Nakashiba ,  Tetsuya Iida ,  Shinichi Watanuki

IPC: G02F1/025 ,  H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L21/3065 ,  H01L21/311 ,  G02F1/015

Abstract: To reduce a production cost of a semiconductor device and provide a semiconductor device having improved characteristics. A grating coupler has a plurality of projections separated from each other in an optical waveguide direction and a slab portion formed between any two of the projections adjacent to each other and formed integrally with them; a MOS optical modulator has a projection extending in the optical waveguide direction and slab portions formed on both sides of the projection, respectively, and formed integrally therewith. The projection of the grating coupler and the MOS optical modulator is formed of a first semiconductor layer, a second insulating layer, and a second semiconductor layer stacked successively on a first insulating layer, while the grating coupler and the MOS optical modulator each have a slab portion formed of the first semiconductor layer.

公开(公告)号：US09977186B2

公开(公告)日：2018-05-22

申请号：US15186610

申请日：2016-06-20

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba ,  Shinichi Watanuki

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/124 ,  G02F1/025 ,  G02B6/136 ,  G02B6/34

CPC classification number: G02B6/122 ,  G02B6/136 ,  G02B6/34 ,  G02B2006/12038 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/12107 ,  G02F1/025

Abstract: A semiconductor device including an optical waveguide and a p-type semiconductor portion is configured as follows. The optical waveguide includes: a first semiconductor layer formed on an insulating layer; an insulating layer formed on the first semiconductor layer; and a second semiconductor layer formed on the insulating layer. The p-type semiconductor portion includes the first semiconductor layer. The film thickness of the p-type semiconductor portion is smaller than that of the optical waveguide. By forming the insulating layer between the first semiconductor layer and the second semiconductor layer, control of the film thicknesses of the optical waveguide and the p-type semiconductor portion is facilitated. Specifically, when the unnecessary second semiconductor layer is removed by etching in a step of forming the p-type semiconductor portion, the insulating layer which is the lower layer functions as an etching stopper, and the film thickness of the p-type semiconductor portion can be easily adjusted.

公开(公告)号：US09927573B2

公开(公告)日：2018-03-27

申请号：US15188914

申请日：2016-06-21

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba ,  Shinichi Watanuki

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/132 ,  G02F1/025 ,  G02F1/015 ,  H01L31/0248

CPC classification number: G02B6/122 ,  G02B6/12004 ,  G02B6/132 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02F1/025 ,  G02F2001/0152 ,  G02F2202/103 ,  G02F2202/104 ,  H01L31/0248

Abstract: An SOI substrate includes a base substrate, a polycrystalline silicon layer formed on the base substrate, an insulating layer formed on the polycrystalline silicon layer, and a semiconductor layer formed on the insulating layer, and optical waveguides are formed in the semiconductor layer of the SOI substrate. Thus, by arranging the polycrystalline silicon layer under the insulating layer, the insulating layer can be made thin. Since the polycrystalline silicon layer includes a plurality of grains (a mass of grains made of a single crystal Si), even when leakage of light is generated beyond the insulating layer, reflection (diffusion) of light can be suppressed. In addition, by arranging the polycrystalline silicon layer under the insulating layer, the insulating layer can be made thin, so that distortion of a substrate can be suppressed.

公开(公告)号：US09793196B2

公开(公告)日：2017-10-17

申请号：US15341332

申请日：2016-11-02

Applicant: Renesas Electronics Corporation

Inventor： Akira Matsumoto ,  Yoshinao Miura ,  Yasutaka Nakashiba

IPC: H01L23/528 ,  H01L23/495 ,  H01L27/088 ,  H01L27/02 ,  H01L29/417 ,  H01L23/485 ,  H01L23/50 ,  H01L23/492 ,  H01L23/00 ,  H01L27/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/778 ,  H01L29/20 ,  H01L23/482 ,  H01L29/205 ,  H01L29/10

CPC classification number: H01L23/49562 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/4805 ,  H01L2224/4813 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction, each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

公开(公告)号：US09721917B2

公开(公告)日：2017-08-01

申请号：US14483300

申请日：2014-09-11

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba

IPC: H01L27/08 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L24/17 ,  H01L23/49838 ,  H01L23/5227 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1713 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.

公开(公告)号：US09632119B2

公开(公告)日：2017-04-25

申请号：US14475623

申请日：2014-09-03

Applicant: Renesas Electronics Corporation

Inventor： Takatsugu Nemoto ,  Yasutaka Nakashiba ,  Takasuke Hashimoto ,  Shinichi Uchida ,  Kazunori Go ,  Hiroshi Oe ,  Noriko Yoshikawa

IPC: G01R21/00 ,  H01F21/00 ,  G01R15/18

CPC classification number: H01L23/5227 ,  G01R15/181 ,  G01R21/00 ,  G01R31/2607 ,  G01R33/06 ,  H01F21/00 ,  H01F27/2804 ,  H01L23/5286 ,  H01L28/10

Abstract: A sensor device includes a printed circuit board, a power line, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first inductor, and the second semiconductor device includes a second inductor. Each inductor is formed using an interconnect layer. The power line extends between the two inductors without overlapping the first and second inductor, when viewed from a direction perpendicular to a main surface of the printed circuit board.