公开(公告)号：US20150248926A1

公开(公告)日：2015-09-03

申请号：US14714722

申请日：2015-05-18

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G11C11/4076 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US20150244370A1

公开(公告)日：2015-08-27

申请号：US14619342

申请日：2015-02-11

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: H03K19/0175 ,  H03K19/00 ,  G11C16/06 ,  G11C11/4063 ,  G11C11/413

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C5/14 ,  G11C7/1084 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/017545

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

Abstract translation: 用于实现高速信令链路终止的本地片上终端控制器同时在布置在同一存储器模块上的多个集成电路存储器装置内和/或在相同的集成电路封装内并联耦合 到高速信令链路。 终端控制总线耦合到模块上的存储器件，并提供端对端控制信号的对等通信。

公开(公告)号：US08990485B2

公开(公告)日：2015-03-24

申请号：US13917396

申请日：2013-06-13

Applicant: Rambus Inc.

Inventor： Brent Haukness ,  Ian Shaeffer

IPC: G06F12/00 ,  G06F12/02 ,  G11C16/32 ,  G11C29/02 ,  G11C29/50 ,  G11C16/04 ,  G11C29/44

CPC classification number: G11C16/32 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C16/04 ,  G11C16/107 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/4402

Abstract: This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly.

Abstract translation: 本公开提供了一种准确地确定与诸如设备，块或页面之类的闪速存储器细分有关的预期交易时间的方法。 通过执行测试事务来对每个这样的单元的每个位进行编程，可以预先确定每个单元的最大预期编程时间并用于调度目的。 例如，在简单的实现中，可以识别相对精确的经验测量的时间限制并用于有效地管理和调度闪速存储器事务，而不等待最终解决写入非响应页面的尝试。 本公开还提供经验测量的最大闪存交易时间的其他用途，包括经由多个存储器模式和优先存储器; 例如，如果需要高性能模式，则可以容忍闪速存储器交易时间的低变化，并且可以相对快速地标记不满足这些原理的单元。

公开(公告)号：US08707110B1

公开(公告)日：2014-04-22

申请号：US14020755

申请日：2013-09-06

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/00

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

Abstract translation: 提供了用于检测和校正存储器系统中的地址错误的系统和方法。 在存储器系统中，存储器件基于通过地址总线发送的地址生成错误检测码，并将错误检测码发送到存储器控制器。 存储器控制器响应于错误检测码向存储器件发送错误指示。 错误指示使存储器件移除接收的地址并防止存储器操作。

公开(公告)号：US20140068169A1

公开(公告)日：2014-03-06

申请号：US13923184

申请日：2013-06-20

Applicant: Rambus Inc.

Inventor： Frederick Ware ,  Craig E. Hampel ,  Ian Shaeffer ,  Scott C. Best

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F13/1684 ,  G06F13/4234 ,  G11C5/00

Abstract: A memory module includes a substrate having signal lines thereon that form a control path and a plurality of data paths. A plurality of memory devices are mounted on the substrate. Each memory device is coupled to the control path and to a distinct data path. The memory module includes control circuitry to enable each memory device to process a distinct respective memory access command in a succession of memory access commands and to output data on the distinct data path in response to the processed memory access command.

Abstract translation: 存储器模块包括其上具有信号线的衬底，其形成控制路径和多个数据路径。 多个存储器件安装在基片上。 每个存储器件耦合到控制路径和不同的数据路径。 存储器模块包括控制电路，以使得每个存储器设备能够在一系列存储器访问命令中处理不同的相应存储器访问命令，并且响应于处理的存储器访问命令在不同的数据路径上输出数据。

公开(公告)号：US20140052934A1

公开(公告)日：2014-02-20

申请号：US13952530

申请日：2013-07-26

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G11C7/10

CPC classification number: G06F13/4068 ,  G06F13/1673 ,  G06F13/1678 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1075 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

Abstract translation: 存储器件或模块在可选命令端口之间进行选择。 具有内存模块的内存系统包含这种内存设备，可支持点对点连接和不同数量模块的高效互连使用。 存储器件和模块可以是可编程的数据宽度。 同一模块上的设备可以配置为选择不同的命令端口，以便于内存线程化。 模块同样可以配置为为同一目的选择不同的命令端口。

公开(公告)号：US20240296088A1

公开(公告)日：2024-09-05

申请号：US18433897

申请日：2024-02-06

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation

公开(公告)号：US20240282357A1

公开(公告)日：2024-08-22

申请号：US18598237

申请日：2024-03-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/00 ,  Y02D30/50

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20240105242A1

公开(公告)日：2024-03-28

申请号：US18214466

申请日：2023-06-26

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C7/22 ,  G11C5/06 ,  G11C11/4063 ,  G11C29/02

CPC classification number: G11C7/22 ,  G11C5/063 ,  G11C11/4063 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C5/04

Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.

公开(公告)号：US20240096387A1

公开(公告)日：2024-03-21

申请号：US18460413

申请日：2023-09-01

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C8/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/49 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.