公开(公告)号：US09444457B2

公开(公告)日：2016-09-13

申请号：US14842899

申请日：2015-09-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H03K19/096 ,  H03K19/00 ,  G06F1/32 ,  H01L29/04 ,  H01L29/24

CPC classification number: H03K19/0008 ,  G06F1/32 ,  H01L29/045 ,  H01L29/24 ,  H03K19/0013

Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.

公开(公告)号：US09443990B2

公开(公告)日：2016-09-13

申请号：US14464966

申请日：2014-08-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Yasuhiko Takemura ,  Tetsuhiro Tanaka ,  Takayuki Inoue ,  Toshihiko Takeuchi ,  Yasumasa Yamane ,  Shunpei Yamazaki

IPC: H03K19/003 ,  H01L21/324 ,  H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  G11C16/04 ,  H01L27/12 ,  H03K19/00 ,  H03K19/177

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/1225 ,  H01L29/4234 ,  H01L29/66833 ,  H03K19/0013 ,  H03K19/17736

Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted is provided. In a semiconductor device including a plurality of transistors arranged in a matrix each including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit that supplies a signal to the gate electrode (e.g., word line driver) is provided with a selection circuit formed of an OR gate, an XOR gate, or the like, whereby potentials of word lines can be simultaneously set higher than potentials of bit lines.

Abstract translation: 提供了其中调整阈值的半导体器件的制造方法。 在包括以矩阵形式排列的多个晶体管的半导体器件中，每个晶体管包括半导体，与该半导体电连接的源极或漏极，栅电极和栅电极与半导体之间的电荷陷阱层，电子被俘获在 通过进行热处理，同时使栅电极的电位比源极或漏极的电位高1秒以上。 通过该过程，阈值增加并且Icut减小。 向门电极（例如字线驱动器）提供信号的电路设置有由或门，异或门等形成的选择电路，由此可以将字线的电位同时设置为高于电位 位线。

公开(公告)号：US09424890B2

公开(公告)日：2016-08-23

申请号：US14951937

申请日：2015-11-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki

IPC: G11C11/24 ,  G11C5/10 ,  H01L27/06 ,  H01L27/108 ,  G11C7/12

CPC classification number: G11C5/10 ,  G11C7/12 ,  G11C11/405 ,  H01L21/8258 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device capable of inhibiting incorrect data readout is provided. In a memory cell including a first transistor, a second transistor, and a third transistor, the potential of a fourth wiring is set to GND when data is written, and the potential is set to VDD when data is read out, for example. Note that the potential of a third wiring is set to GND when data is written and when data is read out, for example. When data is read out, the first transistor is off, so that a first capacitor and a fourth capacitor are connected in series. The potential of a second electrode of the second capacitor increases in this state, and thus part of charges accumulated in the second capacitor transfers to the first capacitor, so that the potential of a node increases.

Abstract translation: 提供能够抑制不正确的数据读出的半导体器件。 在包括第一晶体管，第二晶体管和第三晶体管的存储单元中，例如，当数据被写入时，第四布线的电位被设置为GND，并且例如在读出数据时将电位设置为VDD。 注意，例如，当写入数据和数据被读出时，第三布线的电位被设置为GND。 当读出数据时，第一晶体管截止，使得第一电容器和第四电容器串联连接。 在该状态下，第二电容器的第二电极的电位增加，因此累积在第二电容器中的电荷的一部分转移到第一电容器，使得节点的电位增加。

公开(公告)号：US09391449B2

公开(公告)日：2016-07-12

申请号：US14642002

申请日：2015-03-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Asami Tadokoro

IPC: H04B7/00 ,  H02H9/02 ,  G06K19/07 ,  H01Q1/22

CPC classification number: H02H9/02 ,  G06K19/0701 ,  G06K19/0715 ,  G06K19/0723 ,  H01Q1/2208 ,  H01Q1/2283 ,  Y10T307/858

Abstract: Of a wireless communication system, an RF tag which can operate normally even when a communication distance is extremely short, like the case where the RF tag is in contact with a reader/writer, whereby the reliability is improved. The RF tag which communicates data by wireless communication includes a comparison circuit which compares electric power supplied from outside with reference electric power and a protection circuit portion which is operated when the electric power supplied from outside is higher than the reference electric power in the comparison circuit.

公开(公告)号：US09373643B2

公开(公告)日：2016-06-21

申请号：US14541269

申请日：2014-11-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H04B1/28 ,  H04B1/38 ,  H01L27/12 ,  H01L27/06 ,  H01L29/786 ,  H04B1/40 ,  G06K19/077 ,  H01L29/10

CPC classification number: H01L29/78696 ,  G06K19/07749 ,  G06K19/07773 ,  H01L23/66 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/1033 ,  H01L29/7869 ,  H01L2223/6677 ,  H04B1/40 ,  Y02D70/00

Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.

公开(公告)号：US09350334B2

公开(公告)日：2016-05-24

申请号：US14510310

申请日：2014-10-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H03K3/00 ,  H03K3/356 ,  G11C7/04 ,  G11C14/00 ,  H01L27/105 ,  H01L27/12 ,  H03K3/037 ,  H03K3/286 ,  G11C16/04 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

CPC classification number: H03K3/356104 ,  G11C7/04 ,  G11C14/0063 ,  G11C16/045 ,  G11C2211/4016 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/28202 ,  H01L21/28211 ,  H01L27/105 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/6659 ,  H03K3/0375 ,  H03K3/286 ,  H03K3/356 ,  H03K3/356121 ,  H03K3/356173

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.

公开(公告)号：US09349418B2

公开(公告)日：2016-05-24

申请号：US14582319

申请日：2014-12-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka Yamamoto ,  Kiyoshi Kato

IPC: G11C11/00 ,  G11C11/14 ,  G11C5/14 ,  H01L27/108 ,  H01L27/06 ,  H01L29/786 ,  G11C8/16 ,  G11C11/405 ,  G11C11/408 ,  G11C11/56 ,  H01L27/115

CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C8/16 ,  G11C11/24 ,  G11C11/405 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/565 ,  G11C2207/108 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/1082 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10858 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/786 ,  H01L29/7869

Abstract: A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.

Abstract translation: 可以写入和读取多级数据的新型半导体器件。 半导体器件包括第一至第五晶体管，电容器，位线和电源线。 以通过第一晶体管将第一数据提供给第五晶体管的栅极的方式执行写入操作; 第一个晶体管关闭; 第二数据通过第二晶体管提供给电容器的第二电极，以将第一数据转换为第三数据; 并且使电容器的第二电极电浮动。 电容器的第二个电极通过第三个晶体管初始化为GND。 通过对第四晶体管和第五晶体管的位线进行充电或放电来进行读操作。 第一至第三晶体管优选为氧化物半导体晶体管。

公开(公告)号：US09312269B2

公开(公告)日：2016-04-12

申请号：US14272853

申请日：2014-05-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Tatsuya Onuki

IPC: H01L29/10 ,  H01L29/12 ,  H01L27/115 ,  H01L27/108 ,  G11C11/00 ,  H01L27/105 ,  G11C14/00 ,  H01L27/11

CPC classification number: H01L27/11563 ,  G11C11/005 ,  G11C11/412 ,  G11C14/0054 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/10894 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.

Abstract translation: 具有新型结构的半导体器件，其中提供了即使使用小型化元件来保持数据所需的存储容量。 在半导体器件中，电容器的电极是设置在与晶体管的栅极相同的层中的电极和设置在与晶体管的源极和漏极相同的层中的电极。 此外，在不同的层中设置提供晶体管的栅极的层和连接多个存储器中的晶体管的栅极的布线层。 利用这种结构，可以减小在晶体管的栅极周围形成的寄生电容，并且可以在更大的面积中形成电容器。

公开(公告)号：US09299848B2

公开(公告)日：2016-03-29

申请号：US14645547

申请日：2015-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H01L29/786 ,  H01L27/12 ,  H01L27/115

CPC classification number: H01L29/78648 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/78651 ,  H01L29/7869

Abstract: A semiconductor device with a reduced area is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes a first conductor and a second conductor arranged with a distance therebetween, a first insulator over the first conductor and the second conductor, a semiconductor over the first insulator, a second insulator over the semiconductor, a third conductor over the second insulator, and a fourth conductor and a fifth conductor that are in contact with the semiconductor. The first conductor includes a region not overlapping with the third conductor with the semiconductor therebetween, the first conductor includes a region overlapping with the second conductor with the semiconductor therebetween, and one of a source electrode and a drain electrode of the second transistor is electrically connected to the third conductor of the first transistor.

Abstract translation: 提供了一种面积减小的半导体器件。 半导体器件包括第一晶体管和第二晶体管。 第一晶体管包括第一导体和第二导体，第一导体和第二导体之间具有一定距离，第一绝缘体在第一导体和第二导体之上，第一绝缘体上的半导体，半导体上的第二绝缘体，第二绝缘体上的第三导体 ，以及与半导体接触的第四导体和第五导体。 第一导体包括与第三导体不重叠的区域，其间具有半导体，第一导体包括与第二导体重叠的区域，其间具有半导体，并且第二晶体管的源电极和漏电极中的一个电连接 到第一晶体管的第三导体。

公开(公告)号：US09257569B2

公开(公告)日：2016-02-09

申请号：US14060447

申请日：2013-10-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L29/786 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/1225 ,  H01L27/1156 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78645 ,  H01L29/7869 ,  H01L29/788

Abstract: A semiconductor device includes an oxide layer, a source electrode layer in contact with the oxide layer, a first drain electrode layer in contact with the oxide layer, a second drain electrode layer in contact with the oxide layer, a gate insulating film in contact with the oxide layer, a first gate electrode layer overlapping with the source electrode layer and the first drain electrode layer and overlapping with a top surface of the oxide layer with the gate insulating film interposed therebetween, a second gate electrode layer overlapping with the source electrode layer and the second drain electrode layer and overlapping with the top surface of the oxide layer with the gate insulating film interposed therebetween, and a third gate electrode layer overlapping with a side surface of the oxide layer with the gate insulating film interposed therebetween.

Abstract translation: 半导体器件包括氧化物层，与氧化物层接触的源极电极层，与氧化物层接触的第一漏极电极层，与氧化物层接触的第二漏极电极层，与氧化物层接触的栅极绝缘膜 所述氧化物层与所述源极电极层和所述第一漏极电极层重叠并与所述氧化物层的顶面重叠的第一栅极电极层与所述栅极绝缘膜之间插入，与所述源极电极层重叠的第二栅电极层 所述第二漏极电极层与所述氧化物层的顶面重叠，并且所述栅极绝缘膜与所述第二漏极电极层重叠，并且所述第三栅极电极层与所述氧化物层的侧面重叠，并且所述栅极绝缘膜插入其间。