公开(公告)号：US07621969B2

公开(公告)日：2009-11-24

申请号：US11887212

申请日：2006-03-13

申请人： Mutsumi Masumoto ,  Katsumi Terada

发明人： Mutsumi Masumoto ,  Katsumi Terada

IPC分类号： H01L21/00

CPC分类号： H01L21/67109 ,  H01L21/563 ,  H01L21/67144 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/75 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/15788 ,  Y10T29/41 ,  H01L2924/00

摘要： A mounting system is provided with a substrate loader section, a chip mounting section, and a substrate unloader section for sequentially taking out substrates whereupon chips are mounted. The mounting system is characterized in that the substrate loader section is provided with an oven capable of heat insulating a substrate together with a substrate magazine capable of containing a plurality of substrates, a stage heater for heating/heat insulating a substrate is provided, respectively, at a substrate conveying portion from a substrate waiting stage for the chip mounting section to the chip mounting section, at the chip mounting section, and at a substrate conveying portion from the chip mounting section to the substrate unloader section, and the substrate unloader section is provided with an oven capable of heat insulating a substrate together with a substrate magazine capable of containing a plurality of substrates whereupon chips are mounted. The substrate can be sustained at a desirable temperature over the substantially entire mounting process having a series of steps, and in particular, occurrence of problems ascribed to moisture absorption can be suppressed or prevented.

摘要翻译： 安装系统设置有基板装载部分，芯片安装部分和基板卸载部分，用于顺序取出安装芯片的基板。 安装系统的特征在于，基板装载部分设置有能够将基板与能够容纳多个基板的基板隔套一起隔热的烘箱，分别设置用于加热/隔热基板的台加热器， 在从芯片安装部的基板等待台到芯片安装部，芯片安装部以及从芯片安装部到基板卸载部的基板输送部的基板输送部，基板卸载部是 提供了能够将基板与能够容纳多个基板并因此安装芯片的基板隔套一起烘烤的炉。 可以在具有一系列步骤的基本上整个安装过程中将基材维持在期望的温度，并且特别地，可以抑制或防止归因于吸湿的问题的发生。

公开(公告)号：US07521291B2

公开(公告)日：2009-04-21

申请号：US11552351

申请日：2006-10-24

申请人： Mutsumi Masumoto

发明人： Mutsumi Masumoto

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S101 in which the molding is half-cut along the cutting plane; a de-flashing processing step S102 in which the burrs on the cut portion of the half-cut molding are removed; and a second singulation processing step S103 in which the de-flashed molding is completely cut along the cutting plane.

摘要翻译： 本发明的目的是提供一种半导体器件制造方法，通过该方法可以抑制毛刺的产生，同时增加封装的单片化速度。 在本发明的QFN封装的制造方法中，通过将具有多个半导体芯片的引线框与树脂一体地密封而成的模制品; 该操作包括以下处理步骤：第一分割处理步骤S101，其中模制件沿切割平面半切; 去除半切成型体的切割部分的毛刺的去闪烁处理步骤S102; 以及第二切割处理步骤S103，其中去闪光成型件沿着切割平面被完全切割。

公开(公告)号：US20070117264A1

公开(公告)日：2007-05-24

申请号：US11538626

申请日：2006-10-04

申请人： Mutsumi Masumoto

发明人： Mutsumi Masumoto

IPC分类号： H01L21/58

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The objective of the invention is to provide a semiconductor device manufacturing method that can suppress the formation of voids in the underfill resin and realize a highly reliable flip-chip assembly. The semiconductor device manufacturing method pertaining to the present invention comprises the following processing steps: a step of operation in which a plurality of electrodes 24, formed in a two-dimensional array on a principal surface 22 of semiconductor chip 20, are connected to corresponding conductive regions 32, 34 on substrate 30, a step of operation in which underfill resin 40 is supplied between the principal surface of the semiconductor chip and the substrate, and a step of operation in which the semiconductor chip and substrate with supplied underfill resin 40 are exposed to atmospheric pressure.

摘要翻译： 本发明的目的是提供一种半导体器件制造方法，其可以抑制底部填充树脂中的空隙的形成，并实现高可靠性的倒装芯片组装。 本发明的半导体器件制造方法包括以下处理步骤：将半导体芯片20的主表面22上形成为二维阵列的多个电极24连接到相应的导电性的工序 在基板30上的区域32,34，在半导体芯片的主表面和基板之间供给底部填充树脂40的操作步骤以及具有供给的底部填充树脂40的半导体芯片和基板暴露的操作步骤 到大气压力。

公开(公告)号：US20070092991A1

公开(公告)日：2007-04-26

申请号：US11552351

申请日：2006-10-24

申请人： Mutsumi Masumoto

发明人： Mutsumi Masumoto

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S101 in which the molding is half-cut along the cutting plane; a de-flashing processing step S102 in which the burrs on the cut portion of the half-cut molding are removed; and a second singulation processing step S103 in which the de-flashed molding is completely cut along the cutting plane.

摘要翻译： 本发明的目的是提供一种半导体器件制造方法，通过该方法可以抑制毛刺的产生，同时增加封装的单片化速度。 在本发明的QFN封装的制造方法中，通过将具有多个半导体芯片的引线框与树脂一体地密封而成的模制品; 该操作包括以下处理步骤：第一分割处理步骤S101，其中模制物沿着切割平面半切; 去除半切成型体的切割部分上的毛刺的去闪处理步骤S102; 以及第二切割处理步骤S103，其中去除的成型体沿着切割平面被完全切割。

公开(公告)号：US06969919B2

公开(公告)日：2005-11-29

申请号：US10865276

申请日：2004-06-10

申请人： Kiyoshi Yajima ,  Mutsumi Masumoto ,  Chihiro Hatano ,  Kimitaka Nishio ,  Noriyuki Kirikae

发明人： Kiyoshi Yajima ,  Mutsumi Masumoto ,  Chihiro Hatano ,  Kimitaka Nishio ,  Noriyuki Kirikae

IPC分类号： C09J11/04 ,  C09J163/00 ,  C09J171/10 ,  C09J201/00 ,  H01L21/301 ,  H01L21/44 ,  H01L21/52 ,  H01L21/58 ,  H01L21/68 ,  H01L21/78 ,  H01L23/29 ,  H01L23/48

CPC分类号： H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/45144 ,  H01L2224/83191 ,  H01L2224/83805 ,  H01L2224/83855 ,  H01L2224/85207 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

摘要： A semiconductor package production method containing a step in which a bond layer made of a single-layer film thermoset bond is provided on the back of a wafer on which many semiconductor devices are formed, a dicing tape is pasted onto its bond layer side, and the bond layer and the wafer are diced simultaneously in order to obtain semiconductor devices with the bond layer, and a step in which the semiconductor devices with the bond layer are detached from the dicing tape and die-attached to interposing substrates serving as bodies to which they are bonded; wherein, the aforementioned film thermoset bond contains an epoxy resin, an epoxy resin hardener, and a phenoxy resin as well as 50-80 wt % of spherical silica, and the bond layer is 100 μm or thicker. A semiconductor device made by this method and a wafer for use with this method.

摘要翻译： 一种半导体封装件的制造方法，其特征在于，在形成有许多半导体器件的晶片的背面设置有由单层膜热固接合而形成的接合层的步骤，将切割带贴合在其接合层侧， 同时切割接合层和晶片以获得具有接合层的半导体器件，并且其中具有接合层的半导体器件与切割带分离并且模具附接到作为其的主体的插入基板的步骤 他们是保税的 其中，上述膜热固性粘合剂含有环氧树脂，环氧树脂固化剂和苯氧基树脂以及50〜80重量％的球形二氧化硅，并且接合层为100μm以上。 通过该方法制造的半导体器件和用于该方法的晶片。

公开(公告)号：US06887778B2

公开(公告)日：2005-05-03

申请号：US10253339

申请日：2002-09-24

申请人： Masako Watanabe ,  Mutsumi Masumoto

发明人： Masako Watanabe ,  Mutsumi Masumoto

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/498 ,  H05K3/34 ,  H01L21/44

CPC分类号： H05K3/3436 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device and its manufacturing method with which the connection reliability can be improved without complicating the manufacturing process. Semiconductor chip 102 is mounted on the principal surface of insulated substrate 104, and a conductive paste containing a heat-curing epoxy resin is supplied to via holes 116 from the back of insulated substrate 104. Then, solder balls 118 are transferred onto the conductive paste of insulated substrate 104, and reflow soldering is applied in order to bond solder balls 118 to insulated substrate 104. During the reflow soldering, the heat-curing epoxy resin forms resin parts 120 around solder balls 118.

摘要翻译： 一种半导体器件及其制造方法，可以在不使制造工艺复杂化的情况下提高连接可靠性。 半导体芯片102安装在绝缘基板104的主表面上，并且含有热固化环氧树脂的导电浆料从绝缘基板104的背面供给到通孔116。 然后，将焊球118转印到绝缘基板104的导电糊料上，并施加回流焊以将焊球118粘合到绝缘基板104。 在回流焊接期间，热固化环氧树脂在焊球118周围形成树脂部分120。

公开(公告)号：US06876077B2

公开(公告)日：2005-04-05

申请号：US10346744

申请日：2003-01-17

申请人： Kensho Murata ,  Mutsumi Masumoto ,  Kenji Masumoto

发明人： Kensho Murata ,  Mutsumi Masumoto ,  Kenji Masumoto

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L23/48

CPC分类号： H05K3/3436 ,  H01L21/56 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K2201/0379 ,  H05K2201/10234 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171

摘要： Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.

摘要翻译： 提高制造称为晶片级CSP的半导体器件的生产率和成本。 与本发明相关的半导体器件的制造方法包含形成布线（18）的每个工艺，其用于将每个电极焊盘（10a）和外部连接端子电连接到晶片（10）的顶部，其上半导体 形成元件，连接通过其上方分开的工艺预成型的导电球，接下来，用树脂（32）覆盖上述晶片，使得导电支撑柱（30）的上部被暴露。 在后面的处理中，焊球（34）被布置为导电支柱上部的外部连接端子，最后，通过沿着上述边界线对上述晶片进行切割而形成半导体元件 所述半导体元件。

公开(公告)号：US20050003577A1

公开(公告)日：2005-01-06

申请号：US10865276

申请日：2004-06-10

申请人： Kiyoshi Yajima ,  Mutsumi Masumoto ,  Chihiro Hatano ,  Kimitaka Nishio ,  Noriyuki Kirikae

发明人： Kiyoshi Yajima ,  Mutsumi Masumoto ,  Chihiro Hatano ,  Kimitaka Nishio ,  Noriyuki Kirikae

IPC分类号： C09J11/04 ,  C09J163/00 ,  C09J171/10 ,  C09J201/00 ,  H01L21/301 ,  H01L21/44 ,  H01L21/52 ,  H01L21/58 ,  H01L21/68 ,  H01L21/78 ,  H01L23/29 ,  H01L23/48

CPC分类号： H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/45144 ,  H01L2224/83191 ,  H01L2224/83805 ,  H01L2224/83855 ,  H01L2224/85207 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

摘要： A semiconductor package production method containing a step in which a bond layer made of a single-layer film thermoset bond is provided on the back of a wafer on which many semiconductor devices are formed, a dicing tape is pasted onto its bond layer side, and the bond layer and the wafer are diced simultaneously in order to obtain semiconductor devices with the bond layer, and a step in which the semiconductor devices with the bond layer are detached from the dicing tape and die-attached to interposing substrates serving as bodies to which they are bonded; wherein, the aforementioned film thermoset bond contains an epoxy resin, an epoxy resin hardener, and a phenoxy resin as well as 50-80 wt % of spherical silica, and the bond layer is 100 μm or thicker. A semiconductor device made by this method and a wafer for use with this method.

公开(公告)号：US06774496B2

公开(公告)日：2004-08-10

申请号：US10391005

申请日：2003-03-18

申请人： Kiyoshi Yajima ,  Mutsumi Masumoto ,  Chihiro Hatano ,  Kimitaka Nishio ,  Noriyuki Kirikae

发明人： Kiyoshi Yajima ,  Mutsumi Masumoto ,  Chihiro Hatano ,  Kimitaka Nishio ,  Noriyuki Kirikae

IPC分类号： H01L2348

CPC分类号： H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/45144 ,  H01L2224/83191 ,  H01L2224/83805 ,  H01L2224/83855 ,  H01L2224/85207 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

摘要： A semiconductor package production method containing a step in which a bond layer made of a single-layer film thermoset bond is provided on the back of a wafer on which many semiconductor devices are formed, a dicing tape is pasted onto its bond layer side, and the bond layer and the wafer are diced simultaneously in order to obtain semiconductor devices with the bond layer, and a step in which the semiconductor devices with the bond layer are detached from the dicing tape and die-attached to interposing substrates serving as bodies to which they are bonded; wherein, the aforementioned film thermoset bond contains an epoxy resin, an epoxy resin hardener, and a phenoxy resin as well as 50-80 wt % of spherical silica, and the bond layer is 100 &mgr;m or thicker. A semiconductor device made by this method and a wafer for use with this method.

摘要翻译： 一种半导体封装件的制造方法，其特征在于，在形成有许多半导体器件的晶片的背面设置有由单层膜热固接合而形成的接合层的步骤，将切割带贴合在其接合层侧， 同时切割接合层和晶片以获得具有接合层的半导体器件，并且其中具有接合层的半导体器件与切割带分离并且模具附接到作为其的主体的插入基板的步骤 他们是保税的 其中，上述膜热固性粘合剂含有环氧树脂，环氧树脂固化剂和苯氧基树脂以及50〜80重量％的球形二氧化硅，并且接合层为100μm以上。 通过该方法制造的半导体器件和用于该方法的晶片。

公开(公告)号：US06525424B2

公开(公告)日：2003-02-25

申请号：US09826269

申请日：2001-04-04

申请人： Kensho Murata ,  Mutsumi Masumoto ,  Kenji Masumoto

发明人： Kensho Murata ,  Mutsumi Masumoto ,  Kenji Masumoto

IPC分类号： H01L2348

CPC分类号： H05K3/3436 ,  H01L21/56 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K2201/0379 ,  H05K2201/10234 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171

摘要： Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.