公开(公告)号：US06887778B2

公开(公告)日：2005-05-03

申请号：US10253339

申请日：2002-09-24

申请人： Masako Watanabe ,  Mutsumi Masumoto

发明人： Masako Watanabe ,  Mutsumi Masumoto

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/498 ,  H05K3/34 ,  H01L21/44

CPC分类号： H05K3/3436 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device and its manufacturing method with which the connection reliability can be improved without complicating the manufacturing process. Semiconductor chip 102 is mounted on the principal surface of insulated substrate 104, and a conductive paste containing a heat-curing epoxy resin is supplied to via holes 116 from the back of insulated substrate 104. Then, solder balls 118 are transferred onto the conductive paste of insulated substrate 104, and reflow soldering is applied in order to bond solder balls 118 to insulated substrate 104. During the reflow soldering, the heat-curing epoxy resin forms resin parts 120 around solder balls 118.

摘要翻译： 一种半导体器件及其制造方法，可以在不使制造工艺复杂化的情况下提高连接可靠性。 半导体芯片102安装在绝缘基板104的主表面上，并且含有热固化环氧树脂的导电浆料从绝缘基板104的背面供给到通孔116。 然后，将焊球118转印到绝缘基板104的导电糊料上，并施加回流焊以将焊球118粘合到绝缘基板104。 在回流焊接期间，热固化环氧树脂在焊球118周围形成树脂部分120。

公开(公告)号：US07847399B2

公开(公告)日：2010-12-07

申请号：US11952836

申请日：2007-12-07

申请人： Mutsumi Masumoto

发明人： Mutsumi Masumoto

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/3128 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32507 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/73204 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/8383 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  H05K1/189 ,  H05K3/244 ,  H05K3/328 ,  H05K3/3463 ,  H05K2201/10674 ,  H05K2203/0285 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/83205

摘要： A semiconductor device has a chip (101) with gold studs (212) assembled on a tape substrate (102), which has solder balls (103) for attachment to external parts. The tape substrate (about 30 to 70 μm thick) has on its first surface first copper contact pads (221) covered with a continuous thin nickel layer (222) of about 0.04 to 0.12 μm thickness. Gold including stud (212) is contacting the nickel. On the second substrate surface are second copper contact pads (231) covered with an alloy layer (about 2 to 3 μm thick) including gold, copper/tin alloys, and copper/nickel/tin alloys; the alloys are metallurgically attached to the second copper pad and substantially free of unalloyed nickel. A reflow body (103) comprising tin is metallurgically attached to the alloy layer of each second pad.

摘要翻译： 半导体器件具有芯片（101），其具有组装在带基板（102）上的金柱（212），其具有用于附接到外部部件的焊球（103）。 带衬底（约30至70μm厚）在其第一表面上具有由约0.04至0.12μm厚度的连续薄镍层（222）覆盖的第一铜接触焊盘（221）。 包括螺柱（212）的金属与镍接触。 在第二基板表面上是由包括金，铜/锡合金和铜/镍/锡合金的合金层（约2至3μm厚）覆盖的第二铜接触焊盘（231） 该合金冶金地附接到第二铜焊盘并基本上不含非合金镍。 包括锡的回流体（103）冶金地附接到每个第二焊盘的合金层。

公开(公告)号：US07023088B2

公开(公告)日：2006-04-04

申请号：US10442298

申请日：2003-05-21

申请人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

发明人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

摘要翻译： 形成在与电极焊盘（2）相适应的位置处具有开口部（3a）的绝缘层（3）。 接着，在绝缘层（3）上形成树脂突起部（4）。 此后，形成抗蚀剂膜，该抗蚀剂膜具有在与开口部分（31a）相适应的区域中形成的开口部分，树脂突出部分（4）和夹在其间的区域。 通过使用抗蚀剂膜作为掩模，通过电解铜电镀形成Cu镀层（6）。

公开(公告)号：US20050037539A1

公开(公告)日：2005-02-17

申请号：US10949386

申请日：2004-09-27

申请人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

发明人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L21/44

CPC分类号： H01L24/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

摘要翻译： 形成在与电极焊盘（2）一致的位置具有开口部（3a）的绝缘层（3）。 接着，在绝缘层（3）上形成树脂突起部（4）。 此后，形成抗蚀剂膜，其具有在与开口部分（3a），树脂突出部分（4）和夹在其间的区域相适应的区域中形成的开口部分。 通过使用抗蚀剂膜作为掩模，通过电解铜电镀形成Cu镀层（6）。

公开(公告)号：US06583483B2

公开(公告)日：2003-06-24

申请号：US09909340

申请日：2001-07-19

申请人： Kenji Masumoto ,  Mutsumi Masumoto ,  Akira Karashima

发明人： Kenji Masumoto ,  Mutsumi Masumoto ,  Akira Karashima

IPC分类号： H01L3100

CPC分类号： H01L24/85 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48486 ,  H01L2224/49107 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/4945 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85191 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

摘要： In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is mounted on insulated substrate 12. Multiple stud bumps are stacked on top of the pads 20a which are located on the inner rows, and these stud bumps comprise stud bump stack 28. Conductive wire 22 connects the lands 18 on the insulated substrate with the corresponding bonding pads 20. The wire is formed with its beginning at the land and its end at the bonding pad. Via the stud bump stacks 28, the ends of conductive wire 22a on the inner pads are in a higher position than the ends of conductive wires 22b on the outer pads, so that the problem of neighboring conductive wires coming into contact does not occur.

摘要翻译： 在本发明的半导体器件10中，接合焊盘20以安装在绝缘基板12上的半导体芯片14的主表面上的交错图案排列。多个柱形突起堆叠在焊盘20a的位于 内部行，并且这些柱形凸块包括柱形凸起叠层28.导电线22将绝缘基板上的焊盘18与相应的焊盘20连接。焊丝的起始部分在焊盘上形成，其端部形成在焊盘处。 通过柱凸块28，内焊盘上的导线22a的端部处于比外焊盘上的导线22b的端部更高的位置，使得不会发生相邻导线接触的问题。

公开(公告)号：US06269999B1

公开(公告)日：2001-08-07

申请号：US09632181

申请日：2000-08-03

申请人： Tomohiro Okazaki ,  Kenji Masumoto ,  Mutsumi Masumoto ,  Katsumi Yamaguchi

发明人： Tomohiro Okazaki ,  Kenji Masumoto ,  Mutsumi Masumoto ,  Katsumi Yamaguchi

IPC分类号： B23K106

CPC分类号： H01L24/81 ,  B23K20/10 ,  H01L24/75 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/75317 ,  H01L2224/7532 ,  H01L2224/75745 ,  H01L2224/81001 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H05K13/0465 ,  H01L2924/00014

摘要： A semiconductor chip mounting method to prevent the occurrence of particles created while mounting the semiconductor chip onto a substrate using ultrasonic thermocompression bonding. The mounting method of the present invention utilizing ultrasonic vibrations involves the following steps: a semiconductor chip having conductive bumps on its main surface is held by its back via an elastic film using a suction tool having a suction hole, the semiconductor chip is positioned against a substrate provided with connection wires corresponding to said conductive bumps, and the semiconductor chip is mounted onto the substrate in such a manner that the conductive bumps connect to said connection wires, and ultrasonic vibrations are applied from the suction tool to the semiconductor chip via said film while said semiconductor chip is being pressed against said substrate in order to bond said conductive bumps with said connection wires.

摘要翻译： 一种半导体芯片安装方法，用于防止在使用超声波热压接将半导体芯片安装到基板上时产生的颗粒。 利用超声波振动的本发明的安装方法包括以下步骤：在其主表面上具有导电凸块的半导体芯片通过使用具有抽吸孔的抽吸工具的弹性膜由其背面保持，半导体芯片被定位成 衬底，其具有与所述导电凸块相对应的连接线，并且半导体芯片以这样的方式安装到衬底上，使得导电凸块连接到所述连接线，并且超声波振动通过所述膜从吸入工具施加到半导体芯片 同时所述半导体芯片被压在所述基板上，以便用所述连接线将所述导电凸块接合。

公开(公告)号：US08115310B2

公开(公告)日：2012-02-14

申请号：US12482855

申请日：2009-06-11

申请人： Kenji Masumoto ,  Mutsumi Masumoto

发明人： Kenji Masumoto ,  Mutsumi Masumoto

IPC分类号： H01L23/48

CPC分类号： H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16057 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

摘要翻译： 半导体器件组件可以包括半导体芯片，接收衬底和插入在半导体芯片和接收衬底之间的间隔结构。 间隔件在柱和粘结指之间提供了一个空余的空余物，用于过剩的导电材料，否则可能会从柱和键指之间流出，导致导电短路。 间隔件还可以提供柱和粘合指之间的偏移。

公开(公告)号：US20090011538A1

公开(公告)日：2009-01-08

申请号：US11887212

申请日：2006-03-13

申请人： Mutsumi Masumoto ,  Katsumi Terada

发明人： Mutsumi Masumoto ,  Katsumi Terada

IPC分类号： H01L21/00

CPC分类号： H01L21/67109 ,  H01L21/563 ,  H01L21/67144 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/75 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/15788 ,  Y10T29/41 ,  H01L2924/00

摘要： A mounting system is provided with a substrate loader section, a chip mounting section, and a substrate unloader section for sequentially taking out substrates whereupon chips are mounted. The mounting system is characterized in that the substrate loader section is provided with an oven capable of heat insulating a substrate together with a substrate magazine capable of containing a plurality of substrates, a stage heater for heating/heat insulating a substrate is provided, respectively, at a substrate conveying portion from a substrate waiting stage for the chip mounting section to the chip mounting section, at the chip mounting section, and at a substrate conveying portion from the chip mounting section to the substrate unloader section, and the substrate unloader section is provided with an oven capable of heat insulating a substrate together with a substrate magazine capable of containing a plurality of substrates whereupon chips are mounted. The substrate can be sustained at a desirable temperature over the substantially entire mounting process having a series of steps, and in particular, occurrence of problems ascribed to moisture absorption can be suppressed or prevented.

摘要翻译： 安装系统设置有基板装载部分，芯片安装部分和基板卸载部分，用于顺序取出安装芯片的基板。 安装系统的特征在于，基板装载部分设置有能够将基板与能够容纳多个基板的基板隔套一起隔热的烘箱，分别设置用于加热/隔热基板的台加热器， 在从芯片安装部的基板等待台到芯片安装部，芯片安装部以及从芯片安装部到基板卸载部的基板输送部的基板输送部，基板卸载部是 提供了能够将基板与能够容纳多个基板并因此安装芯片的基板隔套一起烘烤的炉。 可以在具有一系列步骤的基本上整个安装过程中将基材维持在期望的温度，并且特别地，可以抑制或防止归因于吸湿的问题的发生。

公开(公告)号：US07459339B2

公开(公告)日：2008-12-02

申请号：US11538626

申请日：2006-10-04

申请人： Mutsumi Masumoto

发明人： Mutsumi Masumoto

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The objective of the invention is to provide a semiconductor device manufacturing method that can suppress the formation of voids in the underfill resin and realize a highly reliable flip-chip assembly. The semiconductor device manufacturing method pertaining to the present invention comprises the following processing steps: a step of operation in which a plurality of electrodes 24, formed in a two-dimensional array on a principal surface 22 of semiconductor chip 20, are connected to corresponding conductive regions 32, 34 on substrate 30, a step of operation in which underfill resin 40 is supplied between the principal surface of the semiconductor chip and the substrate, and a step of operation in which the semiconductor chip and substrate with supplied underfill resin 40 are exposed to atmospheric pressure.

摘要翻译： 本发明的目的是提供一种半导体器件制造方法，其可以抑制底部填充树脂中的空隙的形成，并实现高可靠性的倒装芯片组装。 本发明的半导体器件制造方法包括以下处理步骤：将半导体芯片20的主表面22上形成为二维阵列的多个电极24连接到相应的导电性的工序 在基板30上的区域32,34，在半导体芯片的主表面和基板之间供给底部填充树脂40的操作步骤以及具有供给的底部填充树脂40的半导体芯片和基板暴露的操作步骤 到大气压力。

公开(公告)号：US20070132075A1

公开(公告)日：2007-06-14

申请号：US11299594

申请日：2005-12-12

申请人： Mutsumi Masumoto

发明人： Mutsumi Masumoto

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L21/6835 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device (100) has one or more semiconductor chips (110) with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments (111) separated from the chip by gaps (120); the segments have first and second surfaces, wherein the second surfaces (111b) are coplanar (130) with the passive chip surface (101b). Conductive connectors span from the chip contact pads to the respective first segment surface. Polymeric encapsulation compound (150) covers the active chip surface, the connectors, and the first segment surfaces, and are filling the gaps so that the compound forms surfaces coplanar (130) with the passive chip surface and the second segment surfaces. In this structure, the device thickness may be only about 250 μm. Reflow metals may be on the passive chip surface and the second segment surfaces.

摘要翻译： 半导体器件（100）具有一个或多个具有有源和无源表面的半导体芯片（110），其中所述有源表面包括接触焊盘。 该装置还具有通过间隙（120）从芯片分离的多个金属段（111）。 所述段具有第一和第二表面，其中所述第二表面（111b）与所述无源芯片表面（101b）共面（130）。 导电连接器跨越从芯片接触焊盘到相应的第一段表面。 聚合物封装化合物（150）覆盖有源芯片表面，连接器和第一分段表面，并且填充间隙使得化合物与无源芯片表面和第二分段表面共面（130）形成表面。 在该结构中，器件厚度可以仅为约250μm。 回流金属可能在无源芯片表面和第二段表面上。